Document the R-Car V3H (R8A77980) SoC in the Renesas SDHI bindings.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>

The WARN can never trigger because we limited the max_seg number in
renesas_sdhi_of_data already. Remove it and update the comment.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Whitelisting every ES version does not scale. So, we whitelist whole
SoCs independent of ES version. If we need specific handling for an ES
version, we put it to the front, so it will be matched first.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Tested-by: NNguyen Viet Dung <dung.nguyen.aj@renesas.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Sometimes sg->offset is not used for buffer addresses allocated by
dma_map_sg(), so alignment checks should be done on the allocated buffer
addresses. Delete the alignment check for sg->offset that is done before
dma_map_sg(). Instead, it performs the alignment check for
sg->dma_address after dma_map_sg().
Signed-off-by: NMasaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
[Niklas: broke this commit in two and tidied small style issue]
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
[rebased to mmc/next]
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Instead of directly accessing the members of struct scatterlist use the
helpers mmc_get_dma_dir() and sg_dma_address() in
renesas_sdhi_internal_dmac_start_dma(). Based on previous work by
Masaharu Hayakawa.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
[rebased to mmc/next]
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

On some NI 904x devices, using 3.3V signaling for extended periods of
time will physically damage the pads connected to the SDHC, eventually
causing complete failure of the controller. To work around this,
require that we avoid 3.3V signaling.
Signed-off-by: NKyle Roeschley <kyle.roeschley@ni.com>
Signed-off-by: NJennifer Dahm <jennifer.dahm@ni.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Some SD host controllers cannot handle extended use of 3.3V signaling.
To accommodate these controllers, add a capability that requires us to
negotiate the voltage down from 3.3V during card initialization.
Signed-off-by: NKyle Roeschley <kyle.roeschley@ni.com>
Signed-off-by: NJennifer Dahm <jennifer.dahm@ni.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Remove dependencies on HAS_DMA where a Kconfig symbol depends on another
symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST".
In most cases this other symbol is an architecture or platform specific
symbol, or PCI.

Generic symbols and drivers without platform dependencies keep their
dependencies on HAS_DMA, to prevent compiling subsystems or drivers that
cannot work anyway.

This simplifies the dependencies, and allows to improve compile-testing.
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: NMark Brown <broonie@kernel.org>
Acked-by: NRobin Murphy <robin.murphy@arm.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Our set_ios hook is, when the card is power up or down, either doing a full
init or put our controller back into a reset mode.

Since we're also doing that in our runtime_pm hooks, and at possibly much
more often, we can drop it from the set_ios, and either rely on our
runtime_pm hooks or our probe to do it.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

So far, even if our card was not in use, we didn't shut down our MMC
controller, which meant that it was still active and clocking the bus.

While this obviously means that we could save some power there, it also
creates issues when it comes to EMC control since we'll have a perfect peak
at the card clock rate.

Let's implement runtime_pm with autosuspend so that we will shut down the
controller when it's not been in use for quite some time.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In order to improve readibility and reusability, let's move the card setup
to a small function called by our .set_ios hook.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In order to improve readibility and reusability, let's move the clock setup
to a small function called by our .set_ios hook.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In order to improve readibility and reusability, let's move the bus width
setup to a small function called by our .set_ios hook.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

All the other functions in the driver take a struct sunxi_mmc_host pointer.
Let's make it consistent.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Our headers sort algorithm has had pretty chaotic results. Let's fix that.
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now that we have MMC support, enable ext2/3/4 support
in the CI20 defconfig.
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.com>
Acked-by: NJames Hogan <jhogan@kernel.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch uses limit clock rate quirk to reduce clock rate
for "SDR104" mode on IMX side for Marvell 8887
WiFi + Bluetooth chip side, as Marvell does not recommend
to use SDIO at the speed of higher than 150MHz.
Signed-off-by: NDiwakar Sharma <diwakar.sharma@in.bosch.com>
Signed-off-by: NHarish Jenny K N <harish_kandiga@mentor.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds a quirk to limit clock rate which
can be used to reduce the SDIO clock rate for some
chips with broken UHS.
Signed-off-by: NHarish Jenny K N <harish_kandiga@mentor.com>
Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

DDR52 with 8-bit mode should be handled in a different way when
requesting ciu_clk. However DDR50 is used for SDMMC/SDIO and
could never be possible with 8-bit mode. It's trival but misleading.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Cadence sent out an errata report to their customers of this IP.
This errata is not so severe, but the tune request should be sent
twice to avoid the potential issue.

Quote from the report:

Problem Summary
---------------
The IP6116 SD/eMMC PHY design has a timing issue on receive data path.
This issue may lead to an incorrect values of read/write pointers of
the synchronization FIFO. Such a situation can happen at the SDR104
and HS200 tuning procedure when the PHY is requested to change a phase
of sampling clock when moving to the next tuning iteration.

Workarounds
-----------
The following are valid workarounds to resolve the issue:

1. In eMMC mode, software sends tune request twice instead of once at
   each iteration. This means that the clock phase is not changed on
   the second request so there is no potential for clock instability.
2. In SD mode, software must not use the hardware tuning and instead
   perform an almost identical procedure to eMMC, using the HRS34 Tune
   Force register.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Explicitly update the docomentation to support the Meson-AXG platform.
Signed-off-by: NNan Li <nan.li@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NKevin Hilman <khilman@baylibre.com>

Introduce the compatible data to cover the register offset & mask
change of the eMMC controller in Amlogic's Meson-AXG SoC.
Signed-off-by: NNan Li <nan.li@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NKevin Hilman <khilman@baylibre.com>

Update the documentation to list support for Meson-AXG SoC explicitly.
The new binding string is necessary since this SoC introduce a few
IP difference comparing to previous old generation.
Signed-off-by: NNan Li <nan.li@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NKevin Hilman <khilman@baylibre.com>

Since RPMB area is accessible via special ioctl only and boot areas
are unlikely to contain any partitions, exclude them all from listing
in /proc/partitions. This will hide them from various user-level
software (e.g. fdisk), thus avoiding unnecessary access attempts.
Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com>
Signed-off-by: NHarish Jenny K N <harish_kandiga@mentor.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Enable the SD/MMC support, along with DMA engine
support in the CI20 defconfig.
Acked-by: NJames Hogan <jhogan@kernel.org>
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now that we have support for JZ480 SoCs in the MMC driver,
let's enable it on the devicetree.
Acked-by: NJames Hogan <jhogan@kernel.org>
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add the devicetree node to support the MMC host controller
available in JZ480 SoCs.
Acked-by: NJames Hogan <jhogan@kernel.org>
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add the devicetree node to support the DMA controller found
in JZ480 SoCs.
Tested-by: NMathieu Malaterre <malat@debian.org>
Acked-by: NJames Hogan <jhogan@kernel.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Replace dma_request_channel() with dma_request_chan(),
which also supports probing from the devicetree.
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add support for the JZ4780 MMC controller to the jz47xx_mmc driver. There
are a few minor differences from the 4740 to the 4780 that need to be
handled, but otherwise the controllers behave the same. The IREG and IMASK
registers are expanded to 32 bits. Additionally, some error conditions are
now reported in both STATUS and IREG. Writing IREG before reading STATUS
causes the bits in STATUS to be cleared, so STATUS must be read first to
ensure we see and report error conditions correctly.
Signed-off-by: NAlex Smith <alex.smith@imgtec.com>
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The maximum clock rate can be overridden by DT. The clock rate should
be set to the DT-specified value rather than the constant JZ_MMC_CLK_RATE
when this is done. If the maximum clock rate is not set by DT then
mmc->f_max will be set to JZ_MMC_CLK_RATE.
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NAlex Smith <alex.smith@imgtec.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add the devicetree binding for JZ4740/JZ4780 SoC MMC/SD controller.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add support to probe the device via devicetree, which
will be used to support other SoCs such as the JZ4780.

Based on commits from the CI20 repo, by Paul Cercueil
and Alex Smith. Binding document based on work by
Zubair Lutfullah Kakakhel.
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In case a bootloader leaves the device in a bad state,
requesting the interrupt before resetting results in a bad
interrupt loop.
Signed-off-by: NZubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
[Ezequiel: cleanup commit description]
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Instead of accessing the platform data pointer directly,
use the dev_get_platdata() helper.
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Just a minor cleanup to order the headers alphabetically.
This helps prevent merge conflicts.
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Currently, if jz4740_mmc_request_gpios() fails, the driver
tries to release DMA resources. This is wrong because DMA
is requested at a later stage.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
[Ezequiel: cleanup commit message]
Tested-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Respect the actual clock for mmc debugfs to help better debug
the hardware.

mmc_host mmc0: Bus speed (slot 0) = 135475200Hz (slot req 150000000Hz,
actual 135475200HZ div = 0)

cat /sys/kernel/debug/mmc0/ios
clock:          150000000 Hz
actual clock:   135475200 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    9 (mmc HS200)
signal voltage: 0 (1.80 V)
driver type:    0 (driver type B)

Cc: Xiao Yao <xiaoyao@rock-chips.com>
Cc: Ziyuan <xzy.xu@rock-chips.com>
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The use of stack Variable Length Arrays needs to be avoided, as they
can be a vector for stack exhaustion, which can be both a runtime bug
(kernel Oops) or a security flaw (overwriting memory beyond the
stack). Also, in general, as code evolves it is easy to lose track of
how big a VLA can get. Thus, we can end up having runtime failures
that are hard to debug. As part of the directive[1] to remove all VLAs
from the kernel, and build with -Wvla.

Currently driver is using a VLA declared using the number of descriptors.  This
array is used to store integer values and is later used as an argument to
`gpiod_set_array_value_cansleep()` This can be avoided by using
`kmalloc_array()` to allocate memory for the array of integer values.  Memory is
free'd before return from function.

>From the code it appears that it is safe to sleep so we can use GFP_KERNEL
(based _cansleep() suffix of function `gpiod_set_array_value_cansleep()`.

It can be expected that this patch will result in a small increase in overhead
due to the use of `kmalloc_array()`

[1] https://lkml.org/lkml/2018/3/7/621Signed-off-by: NTobin C. Harding <me@tobin.cc>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

On SD 2.00 cards we get lots of these messages:
"mmc0: Got data interrupt 0x00000002 even though no data operation was in progress"
By applying the SDHCI_QUIRK2_STOP_WITH_TC quirk, the messages no longer happen.

A single card claiming to be SD 3.00 compliant also generates the interrupts,
but since the card's manfacturing date is 2002 mar, it's unlikely to really be
SD 3.00. This card is a 8GB SanDisk 'SU08G' 8.0 (SDHC class 4).

This has been reported on Xilinx devices that also use the Arasan IP.
See https://patchwork.kernel.org/patch/8062871/

This has been tested on the Renesas RZ/ND-DB board with the RZ/N1 SoC. The
Arasan IP in this device is version 1.39a and uses a max SD clock of 50MHz and
does not support DDR modes.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>