Amend the atmel mci pin controller to optionally take a pin control
handle and set the state of the pins to:
- "default" on boot, resume and before performing an transfer.
- "sleep" on suspend().

This should make it possible to optimize energy usage for the pins
both for the suspend/resume cycle.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

MMC core already has support for HS400.  Add HS400
support to SDHCI driver.  The SDHC Standard specification
does not define HS400 so consequently HS400 support is
non-standard.  However HS400 is not selected without
the host controller setting the corresponding capability
flags so host controllers not yet supporting HS400
will not be affected.  To support that, a quirk
SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 is introduced to
enable the use of capabilities register reserved bit-63
to indicate HS400 support.

Because HS400 is non-standard for SDHCI, it is possible
that different vendors will do things in different ways.
However HS200 support faced the same issue but currently
there is only one solution.  As such, no attempt has
been made to provide for alternate HS400 solutions except
for SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

1.2V HS200 mode capability is cleared if there is not a voltage
regulator that supports 1.2V.  Do the same for 1.2V HS400 mode.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

supply.vqmmc is used with the IS_ERR macro which means
the value must be valid or an error code.  NULL is
neither, so replace with ERR_PTR(-EINVAL).
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

SDHCI_CTRL_HS_SDR200 is unused.  Remove it.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Synopsys DW_MMC IP core supports Internal DMA Controller with 64-bit address mode from IP version 2.70a onwards.
Updated the driver to support IDMAC 64-bit addressing mode.
Signed-off-by: NPrabu Thangamuthu <prabu.t@synopsys.com>
Reviewed-by: NAlim Akhtar <alim.akhtar@samsung.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

AMD SD controller supports the SDR104 mode, but caps2 can not
be promoted to support hs200 for eMMC.
Signed-off-by: NVincent Wan <vincent.wan@amd.com>
Signed-off-by: NWan Zongshun <mcuos.com@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch is to enable the quirk for AMD sdhci requiring transfer
mode register need to be cleared for commands without data
Signed-off-by: NVincent Wan <vincent.wan@amd.com>
Signed-off-by: NWan Zongshun <mcuos.com@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
Signed-off-by: NVincent Wan <vincent.wan@amd.com>
Signed-off-by: NWan Zongshun <mcuos.com@gmail.com>
Signed-off-by: NArindam Nath <arindam.nath@amd.com>
Tested-by: NVikram B <vikram.b@amd.com>
Tested-by: NRaghavendra Swamy <raghavendra.swamy@amd.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Signed-off-by: NJohan Rudholm <johanru@axis.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

It is possible that we may fail to set the clock rate, if we do so then
log the failure and don't bother reprogramming the IP.
Signed-off-by: NMark Brown <broonie@linaro.org>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add runtime pm support to atmel mci controller.
Use runtime pm APIs to enable/disable atmel mci's clock.
Use runtime autosuspend APIs to enable auto suspend delay.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
[Ulf: Fixed compile error]

The "Badly aligned" tests, test reading/writing with alignments
of 1,2 and 3.  SDHCI now has 64-bit ADMA which has 8-byte
alignment, so extend the tests to test up to 7.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Set a 64-bit DMA mask when using 64-bit DMA.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Set the DMA mask during the first call to ->enable_dma() to
make use of the SDHCI_USE_64_BIT_DMA flag.

This patch is dependent on
commit 8a2f38dd ("ACPI / platform: provide default DMA mask")
which provides the dev->dma_mask pointer without
which dma_set_mask_and_coherent() will always fail.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add 64-bit ADMA support including:
	- add 64-bit ADMA descriptor
	- add SDHCI_USE_64_BIT_DMA flag
	- set upper 32-bits of DMA addresses
	- ability to select 64-bit ADMA
	- ability to use 64-bit ADMA sizes and alignment
	- display "ADMA 64-bit" when host is added

It is assumed that a 64-bit capable device has set a 64-bit DMA mask
and *must* do 64-bit DMA.  A driver has the opportunity to change
that during the first call to ->enable_dma().  Similarly
SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
implement.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Define the ADMA descriptor structure instead of
using manual offsets and casts.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Define all the ADMA constants instead of having numbers
scattered throughout the code.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Define the maximum number of segments instead of
having the constant 128 appearing in the code in
various places.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In preparation for 64-bit ADMA, parameterize ADMA sizes
and alignment.  64-bit ADMA has a larger descriptor
because it contains a 64-bit address instead of a 32-bit
address.  Also data must be 8-byte aligned instead
of 4-byte aligned.  Consequently, sdhci_host members
are added for descriptor, table, and buffer sizes
and alignment.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

It is kernel-style to use 'void *' for anonymous data.
This is being applied to the ADMA bounce buffer which
contains unaligned bytes, and to the ADMA descriptor
table which will contain 32-bit ADMA descriptors
or 64-bit ADMA descriptors when support is added.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In preparation for 64-bit ADMA, separate out code
that touches the ADMA descriptor by adding
sdhci_adma_mark_end().
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In preparation for 64-bit ADMA, rename adma_desc to
adma_table.  That is because members will be added
for descriptor size and table size, so using adma_desc
(which is the table) is confusing.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Rename sdhci_set_adma_desc to sdhci_adma_write_desc and
sdhci_show_adma_error to sdhci_adma_show_error so that
all ADMA functions start with sdhci_adma_.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The intent of the warning is to warn if the ADMA table
overflows.  However there can be one more 'end' entry
so the condition should be adjusted accordingly.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Bytes are being copied from/to a single page.  The intent
of the warning is to warn if the page boundary is crossed.
There are two problems.  First, PAGE_MASK is mistaken for
(PAGE_SIZE - 1).  Secondly, instead of using the number
of bytes to copy, the warning is using the maximum that
that value could be.  Fix both.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The ADMA2 descriptor table size was being calculated incorrectly
Fix it.

Note that it has been wrong for a long time and likely has not
caused any problems because of a combination of 1) not needing
alignment descriptors for block operations 2) more memory being
allocated than was requested 3) the use of
SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC which does not use an extra
descriptor for the end marker.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add support for non-removable slots which have no card detection GPIO
and which should not be polled for a card change.
Signed-off-by: NTimo Kokkonen <timo.kokkonen@offcode.fi>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now that sdhci-pxav3 driver allows to have more than one IP clock defined,
document both clocks and clock-names properties.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Besides the I/O clock, some PXAv3 SDHCI IP also requires a core clock to
be enabled. Add an optional core clock to the corresponding driver.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

With support for more than one clock, we'll need to distinguish between
the clock by name. Change clock probing to first try to get "io" clock
before falling back to unnamed clock.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

As we are using references to the I/O clock throughout the driver,
move it to the private data. Also, in preparation for core clock,
rename it to clk_io.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

sdhci_add_host and sdhci_platfm_init already report failure,
so don't emit error messages when a failure occurs. This prevents
occurences of "deferred" messages when required power supplies
are not ready for operation yet.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

While allocating buffers for CXD data, let's use kzalloc() to make sure
those are zeroed.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Due to previous patches, all callers of mmc_send_cxd_data() now
allocates their buffers from the heap. This enables us to simplify
mmc_send_cxd_data() by removing the support of handling buffers, which
are allocated from the stack.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Previous patches has replaced the calls to mmc_send_ext_csd() into
mmc_get_ext_csd(), thus mmc_send_ext_csd() has become redundant. Let's
remove it.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

By using mmc_get_ext_csd() in favor of mmc_send_ext_csd, we decrease
code duplication.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

By using mmc_get_ext_csd() in favor of mmc_send_ext_csd, we decrease
code duplication.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Callers of mmc_send_ext_csd() will be able to decrease code duplication
by using mmc_get_ext_csd() instead. Let's make it available.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Instead of doing BUG_ON(), return an error code.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>