1. 12 11月, 2019 5 次提交
  2. 11 11月, 2019 15 次提交
  3. 08 11月, 2019 15 次提交
  4. 07 11月, 2019 5 次提交
    • V
      drm/i915: Preload LUTs if the hw isn't currently using them · 0ccc42a2
      Ville Syrjälä 提交于
      The LUTs are single buffered so in order to program them without
      tearing we'd have to do it during vblank (actually to be 100%
      effective it has to happen between start of vblank and frame start).
      We have no proper mechanism for that at the moment so we just
      defer loading them after the vblank waits have happened. That
      is not quite sufficient (especially when committing multiple pipes
      whose vblanks don't line up) so the LUT load will often leak into
      the following frame causing tearing.
      
      However in case the hardware wasn't previously using the LUT we
      can preload it before setting the enable bit (which is double
      buffered so won't tear). Let's determine if we can do such
      preloading and make it happen. Slight variation between the
      hardware requires some platforms specifics in the checks.
      
      Hans is seeing ugly colored flash on VLV/CHV macchines (GPD win
      and Asus T100HA) when the gamma LUT gets loaded for the first
      time as the BIOS has left some junk in the LUT memory.
      
      v2: Deal with uapi vs. hw crtc state split
          s/GCM/CGM/ typo fix
      
      Cc: Hans de Goede <hdegoede@redhat.com>
      Fixes: 051a6d8d ("drm/i915: Move LUT programming to happen after vblank waits")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191030190815.7359-1-ville.syrjala@linux.intel.comTested-by: NHans de Goede <hdegoede@redhat.com>
      Reviewed-by: NHans de Goede <hdegoede@redhat.com>
      0ccc42a2
    • R
      drm/i915: FB backing gem obj should reside in LMEM · 9e678fc9
      Ramalingam C 提交于
      If Local memory is supported by hardware, we want framebuffer backing
      gem objects from local memory.
      
      if the backing obj is not from LMEM, pin_to_display is failed.
      
      v2:
        memory regions are correctly assigned to obj->memory_regions [tvrtko]
        migration failure is reported as debug log [Tvrtko]
      v3:
        Migration is dropped. only error is reported [Daniel]
        mem region check is move to pin_to_display [Chris]
      v4:
        s/dev_priv/i915 [chris]
      v5:
        i915_gem_object_is_lmem is used for detecting the obj mem type. [Matt]
      
      cc: Matthew Auld <matthew.auld@intel.com>
      Signed-off-by: NRamalingam C <ramalingam.c@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191105144414.30470-1-ramalingam.c@intel.com
      9e678fc9
    • C
      drm/i915: Leave the aliasing-ppgtt size alone · 2b0a4fc2
      Chris Wilson 提交于
      The hidden aliasing-ppgtt's size is never revealed, as we only inspect
      the front GTT when engaged. However, we were "fixing" the hidden ppgtt
      to match, with the net result that we ended up leaking the unused
      portion on Braswell were we preallocated the entire set of top level
      PDP, see gen8_preallocate_top_level_pdp().
      
      [   26.025364] DMA-API: pci 0000:00:02.0: device driver has pending DMA allocations while released from device [count=2]
      [   26.025364] One of leaked entries details: [device address=0x0000000230778000] [size=4096 bytes] [mapped with DMA_BIDIRECTIONAL] [mapped as single]
      [   26.025683] WARNING: CPU: 0 PID: 415 at kernel/dma/debug.c:894 dma_debug_device_change+0x1a4/0x1f0
      [   26.025905] Modules linked in: i915(E-) intel_powerclamp(E) nls_ascii(E) nls_cp437(E) crct10dif_pclmul(E) crc32_pclmul(E) vfat(E) crc32c_intel(E) fat(E) ghash_clmulni_intel(E) prime_numbers(E) intel_gtt(E) i2c_algo_bit(E) efi_pstore(E) drm_kms_helper(E) syscopyarea(E) sysfillrect(E) sysimgblt(E) fb_sys_fops(E) evdev(E) drm(E) aesni_intel(E) glue_helper(E) crypto_simd(E) cryptd(E) intel_cstate(E) sg(E) efivars(E) pcspkr(E) video(E) button(E) efivarfs(E) ip_tables(E) x_tables(E) autofs4(E) sd_mod(E) lpc_ich(E) ahci(E) mfd_core(E) i2c_i801(E) libahci(E) i2c_designware_pci(E) i2c_designware_core(E)
      [   26.026613] CPU: 0 PID: 415 Comm: rmmod Tainted: G            E     5.4.0-rc6+ #25
      [   26.026837] Hardware name:  /, BIOS PYBSWCEL.86A.0027.2015.0507.1758 05/07/2015
      [   26.027080] RIP: 0010:dma_debug_device_change+0x1a4/0x1f0
      [   26.027319] Code: 89 54 24 08 e8 ad 60 62 00 48 8b 54 24 08 48 89 c6 41 57 4d 89 e9 49 89 d8 44 89 f1 41 54 48 c7 c7 e0 61 06 82 e8 c1 aa f5 ff <0f> 0b 5a 59 48 83 3c 24 00 0f 85 97 26 00 00 8b 05 77 47 92 01 85
      [   26.027600] RSP: 0018:ffff888228d2fcc8 EFLAGS: 00010282
      [   26.027831] RAX: 0000000000000000 RBX: 0000000230778000 RCX: 0000000000000000
      [   26.028053] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffffed10451a5f8f
      [   26.028279] RBP: ffff88823480c0b0 R08: 0000000000000001 R09: ffffed1046e83eb1
      [   26.028500] R10: ffffed1046e83eb0 R11: ffff88823741f587 R12: ffffffff82067340
      [   26.028725] R13: 0000000000001000 R14: 0000000000000002 R15: ffffffff82067480
      [   26.028952] FS:  00007fdf3ed174c0(0000) GS:ffff888237400000(0000) knlGS:0000000000000000
      [   26.029185] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [   26.029405] CR2: 000055e211109030 CR3: 0000000230139000 CR4: 00000000001006f0
      [   26.029622] Call Trace:
      [   26.029846]  notifier_call_chain+0x67/0xa0
      [   26.030076]  blocking_notifier_call_chain+0x5a/0x80
      [   26.030305]  device_release_driver_internal+0x20d/0x260
      [   26.030535]  driver_detach+0x7b/0xe1
      [   26.030761]  bus_remove_driver+0x8c/0x153
      [   26.030993]  pci_unregister_driver+0x2d/0xf0
      [   26.032603]  i915_exit+0x16/0x1c [i915]
      Reported-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Fixes: 1eda701e ("drm/i915/gtt: Recursive cleanup for gen8")
      References: c082afac ("drm/i915: Move aliasing_ppgtt underneath its i915_ggtt")
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Reviewed-by: NMika Kuoppala <mika.kuoppala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191106221223.7437-1-chris@chris-wilson.co.uk
      2b0a4fc2
    • J
      drm/i915/display: only include intel_dp_link_training.h where needed · 3c954c41
      Jani Nikula 提交于
      The intel_dp_link_training.h include has no need or place in
      intel_display.h. Include it in intel_display.c instead.
      
      Cc: Manasi Navare <manasi.d.navare@intel.com>
      Fixes: eadf6f91 ("drm/i915/display/icl: Enable master-slaves in trans port sync")
      Reviewed-by: NManasi Navare <manasi.d.navare@intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191029103947.7535-1-jani.nikula@intel.com
      3c954c41
    • D
      drm/i915: use might_lock_nested in get_pages annotation · 74ceefd1
      Daniel Vetter 提交于
      So strictly speaking the existing annotation is also ok, because we
      have a chain of
      
      obj->mm.lock#I915_MM_GET_PAGES -> fs_reclaim -> obj->mm.lock
      
      (the shrinker cannot get at an object while we're in get_pages, hence
      this is safe). But it's confusing, so try to take the right subclass
      of the lock.
      
      This does a bit reduce our lockdep based checking, but then it's also
      less fragile, in case we ever change the nesting around.
      Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Will Deacon <will@kernel.org>
      Cc: linux-kernel@vger.kernel.org
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20191104173720.2696-3-daniel.vetter@ffwll.ch
      74ceefd1