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  1. 06 4月, 2019 1 次提交
    • T
      bus: ti-sysc: Handle swsup idle mode quirks · b4a9a7a3
      由 Tony Lindgren 提交于 
      In preparation of dropping interconnect target module platform data in
favor of devicetree based data, we must pass swsup idle quirks to the
platform data functions.

For now, let's only tag the UART modules with the SWSUP_SIDLE_ACT quirk.
The other modules will get tagged with swsup quirks as we drop the
platform data and test the changes.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      b4a9a7a3
  3. 04 4月, 2019 6 次提交
    • T
      bus: ti-sysc: Add quirk handling for external optional functional clock · a54275f4
      由 Tony Lindgren 提交于 
      We cannot access mcpdm registers at all unless there is an optional pdmclk
configured. As this is currently only needed for mcpdm, let's check for
mcpdm in sysc_get_clocks(). If it turns out to be needed for other modules
too, we can add more flags to the quirks table for this.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      a54275f4
    • T
      bus: ti-sysc: Add support for early quirks based on register address · 42b9c5c9
      由 Tony Lindgren 提交于 
      At least mcpdm needs an optional external clock enabled to function and
this clock typically comes from the PMIC. We can detect mcpdm based on
the interconnect target module address and set a quirk flag early.

To do this, let's initialize the clocks a bit later and add a new
function for sysc_init_early_quirks(). Note that we cannot yet enable
the early quirks for mcpdm until the optional external clocks are
handled in the in the following patch.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      42b9c5c9
    • T
      bus: ti-sysc: Move rstctrl reset to happen later · b11c1ea1
      由 Tony Lindgren 提交于 
      We can do the rsstctrl a bit later, but need to deassert rstctrl reset
before the clocks are enabled if asserted. Let's only init restctrl
in sysc_init_resets() and do the reset later on just before we enable
the device clocks.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      b11c1ea1
    • T
      bus: ti-sysc: Manage clocks for the interconnect target module in all cases · 93de83a2
      由 Tony Lindgren 提交于 
      We are currently not managing interconnect target module clocks in the
for legacy platform data based case. This causes a problem for using the
platform data based functions when dropping the platform data for the
interconnect target module configuration.

To avoid a situation where we need to populate the main and optional
clocks also for the platform data based functions, let's just manage the
clocks directly in ti-sysc driver. This means that until the interconnect
target module confugration platform data is dropped our use count for
clk_enable() will be 2 instead of 1.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      93de83a2
    • T
      bus: ti-sysc: Allocate mdata as needed and do platform data based init later · a3e92e7b
      由 Tony Lindgren 提交于 
      The platform data based init functions typically reset the interconnect
target module configure the registers. As we may need the interconnect
target module specific quirks configured based on the revision register,
we want to move the platform data based init to happen later.

Let's allocate mdata as needed so it's available for sysc_legacy_init()
that we call with module clocks enabled from sysc_init_module().
Signed-off-by: NTony Lindgren <tony@atomide.com>
      a3e92e7b
    • T
      bus: ti-sysc: Enable all clocks directly during init to read revision · 1a5cd7c2
      由 Tony Lindgren 提交于 
      The first thing we want to do is just read the module revision register to
be able to configure the module specific quirks and configure the module
registers.

As the interconnect target module may not yet be properly configured and
may need a reset first, we don't want to use pm_runtime_get() at this
point.

To read the revision register, let's just enable the all the clocks for
the interconnect target module during init even if the optional clocks
are not needed. That way we can read the revision register to configure
the quirks needed for PM runtime.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      1a5cd7c2
  5. 01 4月, 2019 5 次提交
  7. 15 3月, 2019 3 次提交
  9. 14 3月, 2019 24 次提交
  11. 13 3月, 2019 1 次提交