1. 26 3月, 2021 1 次提交
  2. 25 3月, 2021 1 次提交
  3. 19 3月, 2021 1 次提交
  4. 16 3月, 2021 1 次提交
  5. 06 3月, 2021 1 次提交
  6. 03 3月, 2021 1 次提交
    • W
      stmmac: intel: Fix mdio bus registration issue for TGL-H/ADL-S · fa706dce
      Wong Vee Khee 提交于
      On Intel platforms which consist of two Ethernet Controllers such as
      TGL-H and ADL-S, a unique MDIO bus id is required for MDIO bus to be
      successful registered:
      
      [   13.076133] sysfs: cannot create duplicate filename '/class/mdio_bus/stmmac-1'
      [   13.083404] CPU: 8 PID: 1898 Comm: systemd-udevd Tainted: G     U            5.11.0-net-next #106
      [   13.092410] Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-S ADP-S DRR4 CRB, BIOS ADLIFSI1.R00.1494.B00.2012031421 12/03/2020
      [   13.105709] Call Trace:
      [   13.108176]  dump_stack+0x64/0x7c
      [   13.111553]  sysfs_warn_dup+0x56/0x70
      [   13.115273]  sysfs_do_create_link_sd.isra.2+0xbd/0xd0
      [   13.120371]  device_add+0x4df/0x840
      [   13.123917]  ? complete_all+0x2a/0x40
      [   13.127636]  __mdiobus_register+0x98/0x310 [libphy]
      [   13.132572]  stmmac_mdio_register+0x1c5/0x3f0 [stmmac]
      [   13.137771]  ? stmmac_napi_add+0xa5/0xf0 [stmmac]
      [   13.142493]  stmmac_dvr_probe+0x806/0xee0 [stmmac]
      [   13.147341]  intel_eth_pci_probe+0x1cb/0x250 [dwmac_intel]
      [   13.152884]  pci_device_probe+0xd2/0x150
      [   13.156897]  really_probe+0xf7/0x4d0
      [   13.160527]  driver_probe_device+0x5d/0x140
      [   13.164761]  device_driver_attach+0x4f/0x60
      [   13.168996]  __driver_attach+0xa2/0x140
      [   13.172891]  ? device_driver_attach+0x60/0x60
      [   13.177300]  bus_for_each_dev+0x76/0xc0
      [   13.181188]  bus_add_driver+0x189/0x230
      [   13.185083]  ? 0xffffffffc0795000
      [   13.188446]  driver_register+0x5b/0xf0
      [   13.192249]  ? 0xffffffffc0795000
      [   13.195577]  do_one_initcall+0x4d/0x210
      [   13.199467]  ? kmem_cache_alloc_trace+0x2ff/0x490
      [   13.204228]  do_init_module+0x5b/0x21c
      [   13.208031]  load_module+0x2a0c/0x2de0
      [   13.211838]  ? __do_sys_finit_module+0xb1/0x110
      [   13.216420]  __do_sys_finit_module+0xb1/0x110
      [   13.220825]  do_syscall_64+0x33/0x40
      [   13.224451]  entry_SYSCALL_64_after_hwframe+0x44/0xae
      [   13.229515] RIP: 0033:0x7fc2b1919ccd
      [   13.233113] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 93 31 0c 00 f7 d8 64 89 01 48
      [   13.251912] RSP: 002b:00007ffcea2e5b98 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
      [   13.259527] RAX: ffffffffffffffda RBX: 0000560558920f10 RCX: 00007fc2b1919ccd
      [   13.266706] RDX: 0000000000000000 RSI: 00007fc2b1a881e3 RDI: 0000000000000012
      [   13.273887] RBP: 0000000000020000 R08: 0000000000000000 R09: 0000000000000000
      [   13.281036] R10: 0000000000000012 R11: 0000000000000246 R12: 00007fc2b1a881e3
      [   13.288183] R13: 0000000000000000 R14: 0000000000000000 R15: 00007ffcea2e5d58
      [   13.295389] libphy: mii_bus stmmac-1 failed to register
      
      Fixes: 88af9bd4 ("stmmac: intel: Add ADL-S 1Gbps PCI IDs")
      Fixes: 8450e23f ("stmmac: intel: Add PCI IDs for TGL-H platform")
      Signed-off-by: NWong Vee Khee <vee.khee.wong@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fa706dce
  7. 18 2月, 2021 1 次提交
  8. 29 1月, 2021 2 次提交
    • V
      stmmac: intel: Configure EHL PSE0 GbE and PSE1 GbE to 32 bits DMA addressing · 7cfc4486
      Voon Weifeng 提交于
      Fix an issue where dump stack is printed and Reset Adapter occurs when
      PSE0 GbE or/and PSE1 GbE is/are enabled. EHL PSE0 GbE and PSE1 GbE use
      32 bits DMA addressing whereas EHL PCH GbE uses 64 bits DMA addressing.
      
      [   25.535095] ------------[ cut here ]------------
      [   25.540276] NETDEV WATCHDOG: enp0s29f2 (intel-eth-pci): transmit queue 2 timed out
      [   25.548749] WARNING: CPU: 2 PID: 0 at net/sched/sch_generic.c:443 dev_watchdog+0x259/0x260
      [   25.558004] Modules linked in: 8021q bnep bluetooth ecryptfs snd_hda_codec_hdmi intel_gpy marvell intel_ishtp_loader intel_ishtp_hid iTCO_wdt mei_hdcp iTCO_vendor_support x86_pkg_temp_thermal kvm_intel dwmac_intel stmmac kvm igb pcs_xpcs irqbypass phylink snd_hda_intel intel_rapl_msr pcspkr dca snd_hda_codec i915 i2c_i801 i2c_smbus libphy intel_ish_ipc snd_hda_core mei_me intel_ishtp mei spi_dw_pci 8250_lpss spi_dw thermal dw_dmac_core parport_pc tpm_crb tpm_tis parport tpm_tis_core tpm intel_pmc_core sch_fq_codel uhid fuse configfs snd_sof_pci snd_sof_intel_byt snd_sof_intel_ipc snd_sof_intel_hda_common snd_sof_xtensa_dsp snd_sof snd_soc_acpi_intel_match snd_soc_acpi snd_intel_dspcfg ledtrig_audio snd_soc_core snd_compress ac97_bus snd_pcm snd_timer snd soundcore
      [   25.633795] CPU: 2 PID: 0 Comm: swapper/2 Tainted: G     U            5.11.0-rc4-intel-lts-MISMAIL5+ #5
      [   25.644306] Hardware name: Intel Corporation Elkhart Lake Embedded Platform/ElkhartLake LPDDR4x T4 RVP1, BIOS EHLSFWI1.R00.2434.A00.2010231402 10/23/2020
      [   25.659674] RIP: 0010:dev_watchdog+0x259/0x260
      [   25.664650] Code: e8 3b 6b 60 ff eb 98 4c 89 ef c6 05 ec e7 bf 00 01 e8 fb e5 fa ff 89 d9 4c 89 ee 48 c7 c7 78 31 d2 9e 48 89 c2 e8 79 1b 18 00 <0f> 0b e9 77 ff ff ff 0f 1f 44 00 00 48 c7 47 08 00 00 00 00 48 c7
      [   25.685647] RSP: 0018:ffffb7ca80160eb8 EFLAGS: 00010286
      [   25.691498] RAX: 0000000000000000 RBX: 0000000000000002 RCX: 0000000000000103
      [   25.699483] RDX: 0000000080000103 RSI: 00000000000000f6 RDI: 00000000ffffffff
      [   25.707465] RBP: ffff985709ce0440 R08: 0000000000000000 R09: c0000000ffffefff
      [   25.715455] R10: ffffb7ca80160cf0 R11: ffffb7ca80160ce8 R12: ffff985709ce039c
      [   25.723438] R13: ffff985709ce0000 R14: 0000000000000008 R15: ffff9857068af940
      [   25.731425] FS:  0000000000000000(0000) GS:ffff985864300000(0000) knlGS:0000000000000000
      [   25.740481] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [   25.746913] CR2: 00005567f8bb76b8 CR3: 00000001f8e0a000 CR4: 0000000000350ee0
      [   25.754900] Call Trace:
      [   25.757631]  <IRQ>
      [   25.759891]  ? qdisc_put_unlocked+0x30/0x30
      [   25.764565]  ? qdisc_put_unlocked+0x30/0x30
      [   25.769245]  call_timer_fn+0x2e/0x140
      [   25.773346]  run_timer_softirq+0x1f3/0x430
      [   25.777932]  ? __hrtimer_run_queues+0x12c/0x2c0
      [   25.783005]  ? ktime_get+0x3e/0xa0
      [   25.786812]  __do_softirq+0xa6/0x2ef
      [   25.790816]  asm_call_irq_on_stack+0xf/0x20
      [   25.795501]  </IRQ>
      [   25.797852]  do_softirq_own_stack+0x5d/0x80
      [   25.802538]  irq_exit_rcu+0x94/0xb0
      [   25.806475]  sysvec_apic_timer_interrupt+0x42/0xc0
      [   25.811836]  asm_sysvec_apic_timer_interrupt+0x12/0x20
      [   25.817586] RIP: 0010:cpuidle_enter_state+0xd9/0x370
      [   25.823142] Code: 85 c0 0f 8f 0a 02 00 00 31 ff e8 22 d5 7e ff 45 84 ff 74 12 9c 58 f6 c4 02 0f 85 47 02 00 00 31 ff e8 7b a0 84 ff fb 45 85 f6 <0f> 88 ab 00 00 00 49 63 ce 48 2b 2c 24 48 89 c8 48 6b d1 68 48 c1
      [   25.844140] RSP: 0018:ffffb7ca800f7e80 EFLAGS: 00000206
      [   25.849996] RAX: ffff985864300000 RBX: 0000000000000003 RCX: 000000000000001f
      [   25.857975] RDX: 00000005f2028ea8 RSI: ffffffff9ec5907f RDI: ffffffff9ec62a5d
      [   25.865961] RBP: 00000005f2028ea8 R08: 0000000000000000 R09: 0000000000029d00
      [   25.873947] R10: 000000137b0e0508 R11: ffff9858643294e4 R12: ffff9858643336d0
      [   25.881935] R13: ffffffff9ef74b00 R14: 0000000000000003 R15: 0000000000000000
      [   25.889918]  cpuidle_enter+0x29/0x40
      [   25.893922]  do_idle+0x24a/0x290
      [   25.897536]  cpu_startup_entry+0x19/0x20
      [   25.901930]  start_secondary+0x128/0x160
      [   25.906326]  secondary_startup_64_no_verify+0xb0/0xbb
      [   25.911983] ---[ end trace b4c0c8195d0ba61f ]---
      [   25.917193] intel-eth-pci 0000:00:1d.2 enp0s29f2: Reset adapter.
      
      Fixes: 67c08ac4 ("net: stmmac: add EHL PSE0 & PSE1 1Gbps PCI info and PCI ID")
      Signed-off-by: NVoon Weifeng <weifeng.voon@intel.com>
      Co-developed-by: NMohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com>
      Signed-off-by: NMohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com>
      Link: https://lore.kernel.org/r/20210126100844.30326-1-mohammad.athari.ismail@intel.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
      7cfc4486
    • W
      stmmac: intel: Add ADL-S 1Gbps PCI IDs · 88af9bd4
      Wong, Vee Khee 提交于
      Added PCI IDs for both Ethernet TSN Controllers on the ADL-S.
      
      Also, skip SerDes programming sequences as these are being carried out
      at the BIOS level for ADL-S.
      Signed-off-by: NWong, Vee Khee <vee.khee.wong@intel.com>
      Link: https://lore.kernel.org/r/20210126085832.3814-1-vee.khee.wong@intel.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
      88af9bd4
  9. 24 12月, 2020 1 次提交
  10. 08 11月, 2020 1 次提交
  11. 31 10月, 2020 1 次提交
  12. 29 9月, 2020 1 次提交
  13. 26 9月, 2020 2 次提交
  14. 01 5月, 2020 5 次提交
  15. 22 4月, 2020 1 次提交
    • V
      net: stmmac: Enable SERDES power up/down sequence · b9663b7c
      Voon Weifeng 提交于
      This patch is to enable Intel SERDES power up/down sequence. The SERDES
      converts 8/10 bits data to SGMII signal. Below is an example of
      HW configuration for SGMII mode. The SERDES is located in the PHY IF
      in the diagram below.
      
      <-----------------GBE Controller---------->|<--External PHY chip-->
      +----------+         +----+            +---+           +----------+
      |   EQoS   | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External |
      |   MAC    |         |xPCS|            |IF |           | PHY      |
      +----------+         +----+            +---+           +----------+
             ^               ^                 ^                ^
             |               |                 |                |
             +---------------------MDIO-------------------------+
      
      PHY IF configuration and status registers are accessible through
      mdio address 0x15 which is defined as mdio_adhoc_addr. During D0,
      The driver will need to power up PHY IF by changing the power state
      to P0. Likewise, for D3, the driver sets PHY IF power state to P3.
      Signed-off-by: NVoon Weifeng <weifeng.voon@intel.com>
      Signed-off-by: NOng Boon Leong <boon.leong.ong@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b9663b7c
  16. 31 3月, 2020 3 次提交
  17. 18 2月, 2020 1 次提交
  18. 07 2月, 2020 1 次提交
  19. 14 1月, 2020 1 次提交
  20. 10 1月, 2020 1 次提交
  21. 14 10月, 2019 1 次提交
  22. 12 9月, 2019 1 次提交
  23. 28 8月, 2019 4 次提交
  24. 28 7月, 2019 1 次提交
    • T
      net: stmmac: Make MDIO bus reset optional · 1a981c05
      Thierry Reding 提交于
      The Tegra EQOS driver already resets the MDIO bus at probe time via the
      reset GPIO specified in the phy-reset-gpios device tree property. There
      is no need to reset the bus again later on.
      
      This avoids the need to query the device tree for the snps,reset GPIO,
      which is not part of the Tegra EQOS device tree bindings. This quiesces
      an error message from the generic bus reset code if it doesn't find the
      snps,reset related delays.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1a981c05
  25. 05 6月, 2019 1 次提交
    • T
      treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 291 · 4fa9c49f
      Thomas Gleixner 提交于
      Based on 2 normalized pattern(s):
      
        this program is free software you can redistribute it and or modify
        it under the terms and conditions of the gnu general public license
        version 2 as published by the free software foundation this program
        is distributed in the hope it will be useful but without any
        warranty without even the implied warranty of merchantability or
        fitness for a particular purpose see the gnu general public license
        for more details the full gnu general public license is included in
        this distribution in the file called copying
      
        this program is free software you can redistribute it and or modify
        it under the terms and conditions of the gnu general public license
        version 2 as published by the free software foundation this program
        is distributed in the hope [that] it will be useful but without any
        warranty without even the implied warranty of merchantability or
        fitness for a particular purpose see the gnu general public license
        for more details the full gnu general public license is included in
        this distribution in the file called copying
      
      extracted by the scancode license scanner the SPDX license identifier
      
        GPL-2.0-only
      
      has been chosen to replace the boilerplate/reference in 57 file(s).
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NAlexios Zavras <alexios.zavras@intel.com>
      Reviewed-by: NAllison Randal <allison@lohutok.net>
      Cc: linux-spdx@vger.kernel.org
      Link: https://lkml.kernel.org/r/20190529141901.515993066@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4fa9c49f
  26. 01 5月, 2019 1 次提交
  27. 30 4月, 2019 1 次提交
  28. 19 4月, 2019 1 次提交
    • S
      stmmac: pci: Adjust IOT2000 matching · e0c1d14a
      Su Bao Cheng 提交于
      Since there are more IOT2040 variants with identical hardware but
      different asset tags, the asset tag matching should be adjusted to
      support them.
      
      For the board name "SIMATIC IOT2000", currently there are 2 types of
      hardware, IOT2020 and IOT2040. The IOT2020 is identified by its unique
      asset tag. Match on it first. If we then match on the board name only,
      we will catch all IOT2040 variants. In the future there will be no other
      devices with the "SIMATIC IOT2000" DMI board name but different
      hardware.
      Signed-off-by: NSu Bao Cheng <baocheng.su@siemens.com>
      Reviewed-by: NJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e0c1d14a
  29. 12 1月, 2019 1 次提交
    • J
      net: stmmac: Fix PCI module removal leak · 6dea7e18
      Jose Abreu 提交于
      Since commit b7d0f08e, the enable / disable of PCI device is not
      managed which will result in IO regions not being automatically unmapped.
      As regions continue mapped it is currently not possible to remove and
      then probe again the PCI module of stmmac.
      
      Fix this by manually unmapping regions on remove callback.
      
      Changes from v1:
      - Fix build error
      
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Fixes: b7d0f08e ("net: stmmac: Fix WoL for PCI-based setups")
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6dea7e18