提交 · b359049f270dcaab8a5bbdbb966594c16caba16c · openeuler / Kernel

08 2月, 2007 1 次提交

[POWERPC] 83xx: Add base support for the MPC8313E RDB · b359049f

由 Kim Phillips 提交于 2月 07, 2007

Add support for the MPC8313E Reference Development Board (RDB).  The board
is a mini-ITX reference board with 128M DDR2, 8M flash, 32M NAND, USB, PCI,
gigabit ethernet, and serial.
Signed-off-by: NWilson Lo <Wilson.Lo@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

b359049f

07 2月, 2007 39 次提交

P

Merge branch 'linux-2.6' · 84232005
由 Paul Mackerras 提交于 2月 07, 2007

84232005

[POWERPC] Make pSeries use the H_BULK_REMOVE hypervisor call · f03e64f2

由 Paul Mackerras 提交于 2月 06, 2007

H_BULK_REMOVE lets us remove 4 entries from the MMU hash table with one
hypervisor call.  This uses it in pSeries_lpar_hpte_invalidate so we
can tear down mappings with fewer hypervisor calls.
Signed-off-by: NPaul Mackerras <paulus@samba.org>

f03e64f2

[POWERPC] Clear RI bit in MSR before restoring r13 when returning to userspace · e56a6e20

由 Paul Mackerras 提交于 2月 07, 2007

Some instruction tracing tools use the RI (recoverable interrupt) bit
in the MSR to indicate when it's safe to single-step. Currently we
clear RI after restoring r13 when returning to userspace. However,
if we single-step past the point where r13 is restored, we'll corrupt
r13 in the exception entry code and not restore it. This moves the
clearing of RI to just before r13 is restored so this doesn't happen.
Signed-off-by: NPaul Mackerras <paulus@samba.org>

e56a6e20

[POWERPC] Fix performance monitor exception · 449d846d

由 Livio Soares 提交于 2月 07, 2007

To the issue: some point during 2.6.20 development, Paul Mackerras
introduced the "lazy IRQ  disabling" patch (very cool work,  BTW).
In that patch, the performance monitor unit exception was marked as
"maskable", in the sense that if interrupts were soft-disabled, that
exception could be ignored.  This broke my PowerPC profiling code.
The symptom that I see is that a varying number of interrupts
(from 0 to $n$, typically closer to 0) get delivered, when, in
reality, it should always be very close to $n$.

The issue stems from the way masking is being done.   Masking in
this fashion seems to  work well with the decrementer and external
interrupts, because they are raised again until "really"  handled.
For the PMU, however, this does not apply (at least on my Xserver
machine with a 970FX processor).  If the PMU exception is not handled,
it will _not_ be re-raised (at least on my machine).  The documentation
states that the PMXE bit in MMCR0 is set to 0 when the PMU exception
is raised.  However, software must re-set the bit to re-enable PMU
exceptions.  If the exception is ignored (as currently) not only is
that interrupt lost, but because software does not re-set PMXE, the
PMU registers are "frozen" forever.

[This patch means that performance monitor exceptions are taken and
handled even if irqs are off, as long as some other interrupt hasn't
come along and caused interrupts to be hard-disabled.  In this sense
the PMU exception becomes like an NMI.  The oprofile code for most
powerpc processors does nothing that is unsafe in an NMI context, but
the Cell oprofile code does a spin_lock_irqsave.  However, that turns
out to be OK because Cell doesn't actually use the performance
monitor exception; performance monitor interrupts come in as a
regular interrupt on Cell, so will be disabled when irqs are off.
 -- paulus.]
Signed-off-by: NPaul Mackerras <paulus@samba.org>

449d846d

[POWERPC] Compile fixes for arch/powerpc dcr code · a2c70211

由 David Gibson 提交于 2月 06, 2007

The new dcr code does not currently compile when configured for native
DCR access on ARCH=powerpc.  This patch fixes the problems.
Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

a2c70211

[POWERPC] Maple: use mmio nvram · 4297c986

由 Nathan Lynch 提交于 2月 05, 2007

Some systems supported by the maple platform (e.g. JS2x blades running
SLOF) are able to use the mmio_nvram backend for reading and writing
nvram.  This is an improvement over the current situation -- no nvram
access from userspace at all.

Select MMIO_NVRAM for the maple platform.

Initialize the mmio_nvram backend from maple setup code.
Signed-off-by: NNathan Lynch <ntl@pobox.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

4297c986

[POWERPC] pasemi: defconfig · 721e0c90

由 Olof Johansson 提交于 2月 04, 2007

Base pasemi defconfig. Nothing special, just the native drivers plus
common PCI-express/PCI cards.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

721e0c90

[POWERPC] pasemi: iommu support · 31c56d82

由 Olof Johansson 提交于 2月 04, 2007

I/O TLB support for PA6T-1682M.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

31c56d82

[POWERPC] pasemi: Configure DMA controller interrupts · f9fba5b7

由 Olof Johansson 提交于 2月 04, 2007

The DMA controller on PWRficient is somewhat special -- has a PCI header
so it looks like it's on the root PCI (-Express) root bus, but it uses
more than the default number of interrupts (and they are hardwired).

We need to wire up all interrupts for the DMA controller. The generic
IRQ code will only map the primary interrupt from the PCI header (128),
so add 129->211 by hand.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

f9fba5b7

[POWERPC] pasemi: SMP timebase sync · c388cfeb

由 Olof Johansson 提交于 2月 04, 2007

Timebase update is simple on PA6T, since global updates can be done from
one core by writing to an SPR.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

c388cfeb

[POWERPC] pasemi: Implement restart · f620be99

由 Olof Johansson 提交于 2月 04, 2007

Implement reset on platforms/pasemi. Default is just to reset the
cpu using the SDC registers.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

f620be99

[POWERPC] pasemi: Idle loops · 1199919b

由 Olof Johansson 提交于 2月 04, 2007

Powersave support on PA6T. Right now it only uses 'doze' mode, and
will default to no savings (spin).
Signed-off-by: NOlof Johansson <olof@lixom.net>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

1199919b

[POWERPC] pasemi: Machine check handler · bfed9d32

由 Olof Johansson 提交于 2月 04, 2007

Print out decoded machine check information on PA6T.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

bfed9d32

[POWERPC] pasemi: UART udbg support · 39c870d5

由 Olof Johansson 提交于 2月 04, 2007

Early debug output for PA Semi UART. Uses the 2.05 CI real mode ops.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

39c870d5

[POWERPC] Assign all PCI busses on G3 Blue & White · a1fdf694

由 Pavel Roskin 提交于 2月 04, 2007

G3 Blue & White is misconfigured by default so that CardBus controllers
in PCI slots don't work.  The PCI bridge is programmed to only allow
access to bus 1 but not higher busses.

The patch forces the PCI busses to be reassigned if a Grackle controller
is found and the machine identifies itself as "PowerMac1,1"
Signed-off-by: NPavel Roskin <proski@gnu.org>
Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

a1fdf694

[POWERPC] Celleb: add celleb_defconfig · 6e47a0f3