1. 27 10月, 2011 3 次提交
  2. 14 8月, 2011 5 次提交
    • A
      mmc: sdhci: use f_max instead of host->clock for timeouts · 65be3fef
      Andy Shevchenko 提交于
      When timeout_clk is calculated the host->clock could be zero.
      So, instead of host->clock the calculation now uses mmc->f_max.
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      65be3fef
    • A
      mmc: sdhci: move timeout_clk calculation farther down · 272308ca
      Andy Shevchenko 提交于
      This moves the calculation below the assignment of mmc->f_max, which
      we need for calculating timeout_clk in the next patch in this series.
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      272308ca
    • A
      mmc: sdhci: check host->clock before using it as a denominator · 78a2ca27
      Andy Shevchenko 提交于
      Sometimes host->clock could be zero which is a legal situation. This
      patch checks host->clock before usage as a denominator when timeout is
      calculated. A similar patch is applied for mmc core (see commit e9b86841,
      "mmc: fix division by zero in MMC core").
      
      Without this patch, the execution of the sdhci_calc_timeout could end up
      with a backtrace:
      
      <0>[    4.014319] divide error: 0000 [#1] PREEMPT SMP
      <4>[    4.014352] Modules linked in: g_ether
      <4>[    4.014376]
      <4>[    4.014393] Pid: 33, comm: kworker/u:2 Not tainted 3.0.0+ #646
      <4>[    4.014421] EIP: 0060:[<c12fa38e>] EFLAGS: 00010046 CPU: 1
      <4>[    4.014449] EIP is at sdhci_calc_timeout+0x2e/0x100
      <4>[    4.014468] EAX: 00000000 EBX: f5930fc8 ECX: 00000000 EDX: 00000000
      <4>[    4.014488] ESI: f5291de8 EDI: f5291db8 EBP: f5291c6c ESP: f5291c50
      <4>[    4.014508]  DS: 007b ES: 007b FS: 00d8 GS: 0000 SS: 0068
      <0>[    4.014529] Process kworker/u:2 (pid: 33, ti=f5290000 task=f53065a0 task.ti=f5290000)
      <0>[    4.014546] Stack:
      <4>[    4.014557]  00000082 c1054fdd f5291c78 04000000 f5930fc8 f5291de8 f5291db8 f5291cac
      <4>[    4.014611]  c12fab7c c107a98b f5291c88 c13b6d3f f593109c f5882000 f5291cac c1054fdd
      <4>[    4.014663]  00000000 00000000 f5882000 00000082 f5930fc8 f5291db8 0000000a f5291ccc
      <0>[    4.014716] Call Trace:
      <4>[    4.014743]  [<c1054fdd>] ? mod_timer+0x11d/0x380
      <4>[    4.014770]  [<c12fab7c>] sdhci_prepare_data+0x2c/0x3a0
      <4>[    4.014798]  [<c107a98b>] ? trace_hardirqs_off+0xb/0x10
      <4>[    4.014827]  [<c13b6d3f>] ? _raw_spin_unlock_irqrestore+0x2f/0x60
      <4>[    4.014854]  [<c1054fdd>] ? mod_timer+0x11d/0x380
      <4>[    4.014880]  [<c12fc7db>] sdhci_send_command+0xdb/0x210
      <4>[    4.014906]  [<c12fd5f3>] sdhci_request+0xc3/0x150
      <4>[    4.014932]  [<c12ec56a>] mmc_start_request+0xda/0x200
      <4>[    4.014960]  [<c120d7c2>] ? __raw_spin_lock_init+0x32/0x60
      <4>[    4.014989]  [<c1066a85>] ? __init_waitqueue_head+0x35/0x50
      <4>[    4.015015]  [<c12ec70b>] mmc_wait_for_req+0x7b/0x90
      <4>[    4.015045]  [<c12f0c67>] mmc_send_cxd_data+0xf7/0x130
      <4>[    4.015076]  [<c12ecbc0>] ? mmc_erase+0x140/0x140
      <4>[    4.015102]  [<c12f139d>] mmc_send_ext_csd+0x1d/0x20
      <4>[    4.015125]  [<c12efef0>] mmc_get_ext_csd+0x70/0x140
      <4>[    4.015151]  [<c12effe8>] mmc_compare_ext_csds+0x28/0x190
      <4>[    4.015176]  [<c12f039f>] mmc_init_card+0x24f/0x650
      <4>[    4.015201]  [<c13b6d5d>] ? _raw_spin_unlock_irqrestore+0x4d/0x60
      <4>[    4.015226]  [<c107fd9c>] ? trace_hardirqs_on_caller+0x11c/0x160
      <4>[    4.015255]  [<c12f09a4>] mmc_attach_mmc+0xa4/0x190
      <4>[    4.015282]  [<c12ee3f0>] mmc_rescan+0x210/0x240
      <4>[    4.015311]  [<c105f9b6>] process_one_work+0x176/0x550
      <4>[    4.015336]  [<c105f93a>] ? process_one_work+0xfa/0x550
      <4>[    4.015360]  [<c12ee1e0>] ? mmc_init_erase+0x140/0x140
      <4>[    4.015385]  [<c1061c2a>] worker_thread+0x12a/0x2c0
      <4>[    4.015410]  [<c1061b00>] ? manage_workers.clone.18+0x100/0x100
      <4>[    4.015437]  [<c1066244>] kthread+0x74/0x80
      <4>[    4.015463]  [<c10661d0>] ? __init_kthread_worker+0x60/0x60
      <4>[    4.015490]  [<c13b7dfa>] kernel_thread_helper+0x6/0xd
      <0>[    4.015507] Code: 57 89 d7 56 53 89 c3 83 ec 10 8b 40 04 8b 72 28 f6 c4 10 89 45 f0 0f 85 91 00 00 00 85 f6 0f 84 c1 00 00 00 8b 4e 04 31 d2 89 c8 <f7> 73 58 ba d3 4d 62 10 89 c1 8b 06 f7 e2 c1 ea 06 01 d1 f7 45
      <0>[    4.015829] EIP: [<c12fa38e>] sdhci_calc_timeout+0x2e/0x100 SS:ESP 0068:f5291c50
      Reported-by: NAlexander Shishkin <alexander.shishkin@linux.intel.com>
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      78a2ca27
    • A
      mmc: Revert "mmc: sdhci: Fix SDHCI_QUIRK_TIMEOUT_USES_SDCLK" · 83cbcd93
      Andy Shevchenko 提交于
      This reverts commit 4b01681c, which introduced a new potential
      divide by zero in the process of fixing one.  The subsequent commits
      attempt to fix the issue properly.
      Signed-off-by: NChris Ball <cjb@laptop.org>
      83cbcd93
    • A
      mmc: sdhci: fix retuning timer wrongly deleted in sdhci_tasklet_finish · 78869618
      Aaron Lu 提交于
      Currently, the retuning timer for retuning mode 1 will be deleted in
      function sdhci_tasklet_finish after a mmc request done, which will make
      retuning timing never trigger again. This patch fixed this problem.
      Signed-off-by: NAaron Lu <Aaron.Lu@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      78869618
  3. 21 7月, 2011 2 次提交
  4. 26 5月, 2011 3 次提交
  5. 25 5月, 2011 15 次提交
    • P
      mmc: sdhci: add hooks for setting UHS in platform specific code · 6322cdd0
      Philip Rakity 提交于
      Allow platform specific code to set UHS registers if
      implementation requires speciial platform specific handling
      Signed-off-by: NPhilip Rakity <prakity@marvell.com>
      Reviewed-by: NArindam Nath <arindam.nath@amd.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      6322cdd0
    • A
      mmc: sdhci: add support for retuning mode 1 · cf2b5eea
      Arindam Nath 提交于
      Host Controller v3.00 can support retuning modes 1,2 or 3 depending on
      the bits 46-47 of the Capabilities register. Also, the timer count for
      retuning is indicated by bits 40-43 of the same register. We initialize
      timer_list for retuning the first time we execute tuning procedure. This
      condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since
      retuning mode 1 sets a limit of 4MB on the maximum data length, we set
      max_blk_count appropriately. Once the tuning timer expires, we set
      SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning
      procedure before sending the next command. We need to restore mmc_request
      structure after executing retuning procedure since host->mrq is used
      inside the procedure to send CMD19. We also disable and re-enable this
      flag during suspend and resume respectively, as per the spec v3.00.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      cf2b5eea
    • A
      mmc: sdhci: add support for programmable clock mode · c3ed3877
      Arindam Nath 提交于
      Host Controller v3.00 supports programmable clock mode as an optional
      feature. The support for this mode is indicated by non-zero value in
      bits 48-55 of the Capabilities register. If supported, the actual
      value of Clock Multiplier is one more than the value provided in the
      bit fields. We only set Clock Generator Select (bit 5) and SDCLK
      Frequency Select (bits 8-15) of the Clock Control register in case
      Preset Value Enable is not set, otherwise these fields are automatically
      set by the Host Controller based on the UHS mode selected. Also, since
      the maximum and minimum clock frequency in this mode can be
      (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively,
      f_max and f_min have been recalculated to reflect this change.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      c3ed3877
    • A
      mmc: sdhci: enable preset value after uhs initialization · 4d55c5a1
      Arindam Nath 提交于
      According to the Host Controller spec v3.00, setting Preset Value Enable
      in the Host Control2 register lets SDCLK Frequency Select, Clock Generator
      Select and Driver Strength Select to be set automatically by the Host
      Controller based on the UHS-I mode set. This patch enables this feature.
      Since Preset Value Enable makes sense only for UHS-I cards, we enable this
      feature after successfull UHS-I initialization. We also reset Preset Value
      Enable next time before initialization.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      4d55c5a1
    • A
      mmc: sd: add support for tuning during uhs initialization · b513ea25
      Arindam Nath 提交于
      Host Controller needs tuning during initialization to operate SDR50
      and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is
      indicated by bit 45 of the Host Controller Capabilities register.
      A new command CMD19 has been defined in the Physical Layer spec
      v3.01 to request the card to send tuning pattern.
      
      We enable Buffer Read Ready interrupt at the very begining of tuning
      procedure, because that is the only interrupt generated by the Host
      Controller during tuning. We program the block size to 64 in the
      Block Size register. We make sure that DMA Enable and Multi Block
      Select in the Transfer Mode register are set to 0 before actually
      sending CMD19. The tuning block is sent by the card to the Host
      Controller using DAT lines, so we set Data Present Select (bit 5) in
      the Command register. The Host Controller is responsible for doing
      the verfication of tuning block sent by the card at the hardware
      level. After sending CMD19, we wait for Buffer Read Ready interrupt.
      In case we don't receive an interrupt after the specified timeout
      value, we fall back on fixed sampling clock by setting Execute
      Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2
      register to 0. Before exiting the tuning procedure, we disable Buffer
      Read Ready interrupt and re-enable other interrupts.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      b513ea25
    • A
      mmc: sd: set current limit for uhs cards · 5371c927
      Arindam Nath 提交于
      We decide on the current limit to be set for the card based on the
      Capability of Host Controller to provide current at 1.8V signalling,
      and the maximum current limit of the card as indicated by CMD6
      mode 0. We then set the current limit for the card using CMD6 mode 1.
      As per the Physical Layer Spec v3.01, the current limit switch is
      only applicable for SDR50, SDR104, and DDR50 bus speed modes. For
      other UHS-I modes, we set the default current limit of 200mA.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      5371c927
    • A
      mmc: sd: add support for uhs bus speed mode selection · 49c468fc
      Arindam Nath 提交于
      This patch adds support for setting UHS-I bus speed mode during UHS-I
      initialization procedure. Since both the host and card can support
      more than one bus speed, we select the highest speed based on both of
      their capabilities. First we set the bus speed mode for the card using
      CMD6 mode 1, and then we program the host controller to support the
      required speed mode. We also set High Speed Enable in case one of the
      UHS-I modes is selected. We take care to reset SD clock before setting
      UHS mode in the Host Control2 register, and then re-enable it as per
      the Host Controller spec v3.00. We then set the clock frequency for
      the UHS-I mode selected.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      49c468fc
    • A
      mmc: sdhci: reset sdclk before setting high speed enable · 758535c4
      Arindam Nath 提交于
      As per Host Controller spec v3.00, we reset SDCLK before setting
      High Speed Enable, and then set it back to avoid generating clock
      gliches. Before enabling SDCLK again, we make sure the clock is
      stable, so we use sdhci_set_clock().
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      758535c4
    • A
      mmc: sd: add support for driver type selection · d6d50a15
      Arindam Nath 提交于
      This patch adds support for setting driver strength during UHS-I
      initialization procedure. Since UHS-I cards set S18A (bit 24) in
      response to ACMD41, we use this as a base for UHS-I initialization.
      We modify the parameter list of mmc_sd_get_cid() so that we can
      save the ROCR from ACMD41 to check whether bit 24 is set.
      
      We decide whether the Host Controller supports A, C, or D driver
      type depending on the Capabilities register. Driver type B is
      suported by default. We then set the appropriate driver type for
      the card using CMD6 mode 1. As per Host Controller spec v3.00, we
      set driver type for the host only if Preset Value Enable in the
      Host Control2 register is not set. SDHCI_HOST_CONTROL has been
      renamed to SDHCI_HOST_CONTROL1 to conform to the spec.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      d6d50a15
    • A
      mmc: sd: add support for signal voltage switch procedure · f2119df6
      Arindam Nath 提交于
      Host Controller v3.00 adds another Capabilities register. Apart
      from other things, this new register indicates whether the Host
      Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
      doesn't mention about explicit support for SDR12 and SDR25 UHS-I
      modes, so the Host Controller v3.00 should support them by default.
      Also if the controller supports SDR104 mode, it will also support
      SDR50 mode as well. So depending on the host support, we set the
      corresponding MMC_CAP_* flags. One more new register. Host Control2
      is added in v3.00, which is used during Signal Voltage Switch
      procedure described below.
      
      Since as per v3.00 spec, UHS-I supported hosts should set S18R
      to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
      need to set XPC (bit 28) of OCR in case the host can supply >150mA.
      This support is indicated by the Maximum Current Capabilities
      register of the Host Controller.
      
      If the response of ACMD41 has both CCS and S18A set, we start the
      signal voltage switch procedure, which if successfull, will switch
      the card from 3.3V signalling to 1.8V signalling. Signal voltage
      switch procedure adds support for a new command CMD11 in the
      Physical Layer Spec v3.01. As part of this procedure, we need to
      set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
      if remains set after 5ms, means the switch to 1.8V signalling is
      successfull. Otherwise, we clear bit 24 of OCR and retry the
      initialization sequence. When we remove the card, and insert the
      same or another card, we need to make sure that we start with 3.3V
      signalling voltage. So we call mmc_set_signal_voltage() with
      MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
      voltage before we actually start initializing the card.
      
      Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
      on mmp2 in SDMA mode.
      Signed-off-by: NArindam Nath <arindam.nath@amd.com>
      Reviewed-by: NPhilip Rakity <prakity@marvell.com>
      Tested-by: NPhilip Rakity <prakity@marvell.com>
      Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      f2119df6
    • T
      mmc: sdhci: Fix read-only detection with JMicron 388 chip · 82b0e23a
      Takashi Iwai 提交于
      On HP laptops with JMicron 388 chip, the write-locked SD card isn't
      detected correctly as read-only in many cases.  This is because the
      PRESENT_STATE register becomes unsable just after plugging, and it
      returns the WRITE_PROTECT bit wrongly at the first read.
      
      This patch fixes the read-only detection by adding a new sdhci quirk
      indicating to check the register more intensively with a relatively
      long delay.
      
      The patch is tested with 2.6.39-rc4 kernel.
      
      Cc: Aries Lee <arieslee@jmicron.com>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      82b0e23a
    • P
      mmc: sdhci: Add pre and post reset processing for chip specific reset · 393c1a34
      Philip Rakity 提交于
      Marvell pxa controllers have private registers that may need to be
      modified before and after a reset is done.
      
      For example, the SD reset operation, RESET_ALL, will reset the private
      registers to their default state.  This will cause the clock adjustment
      registers that may have been programmed to have incorrect values.
      
      RESET_DATA sometimes needs to be delayed before the reset is done
      (depending on SoC) to enable any transactions being handled by the
      SDIO card to be completed.  Needed in pre SD 3.0 silicon to handle
      clock gating.
      
      Implement hooks to allow this to happen.
      Signed-off-by: NPhilip Rakity <prakity@marvell.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      393c1a34
    • M
      mmc: sdhci: Fix SDHCI_QUIRK_TIMEOUT_USES_SDCLK · 4b01681c
      Mark Brown 提交于
      Commit 373e6a (mmc: sdhci: R1B command handling + MMC_CAP_ERASE) moved the
      handling of SDHCI_QUIRK_TIMEOUT_USES_SDCLK from sdhci_calc_timeout() to
      sdhci_add_host(). This causes division by zero errors on at least the S3C
      SDHCI controller as the quirk implementation needs host->clock set to work
      but host->clock has not been set when sdhci_add_host() is called.
      
      Fix this by backing out that portion of the change, the clock may vary at
      runtime anyway. It does occur to me that we may want to move the quirk to
      where we set the clock but this seems more invasive and I'm concerned
      about undesirable side effects.
      Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Andrei Warkentin <andreiw@motorola.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      4b01681c
    • M
      mmc: sdhci: work around broken dma boundary behavior · f6a03cbf
      Mikko Vinni 提交于
      Some SD host controllers (noticed on an integrated JMicron SD reader on an
      HP Pavilion dv5-1250eo laptop) don't update the dma address register before
      signaling a dma interrupt due to a dma boundary. Update the register
      manually to the next boundary (by default 512KiB), at which the transfer
      stopped.
      
      As long as each transfer is at most 512KiB in size (guaranteed by a BUG_ON
      in sdhci_prepare_data()) and the boundary is kept at the default value,
      this fix is needed at most once per transfer. Smaller boundaries are taken
      care of by counting the transferred bytes.
      
      Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28462Signed-off-by: NMikko Vinni <mmvinni@yahoo.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      f6a03cbf
    • A
      mmc: sdhci: R1B command handling + MMC_CAP_ERASE. · a3c7778f
      Andrei Warkentin 提交于
      ERASE command needs R1B response, so fix R1B-type command
      handling for SDHCI controller. For non-DAT commands using a busy
      response, the cmd->cmd_timeout_ms (in ms) field is used for timeout
      calculations.
      
      Based on patch by Chuanxiao Dong <chuanxiao.dong@intel.com>
      Signed-off-by: NAndrei Warkentin <andreiw@motorola.com>
      Signed-off-by: NChris Ball <cjb@laptop.org>
      a3c7778f
  6. 28 4月, 2011 2 次提交
  7. 09 1月, 2011 4 次提交
  8. 23 11月, 2010 1 次提交
  9. 08 11月, 2010 1 次提交
  10. 23 10月, 2010 4 次提交