Generated by: scripts/checkincludes.pl
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Remove all but the first include of reg_helper.h and core_types.h
from dcn201_clk_mgr.c.
Reported-by: NZeal Robot <zealci@zte.com.cn>
Signed-off-by: NLv Ruyi <lv.ruyi@zte.com.cn>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Got Werror when building with Clang-13:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:195:2:
error: variable 'ts' is used uninitialized whenever switch default is
taken [-Werror,-Wsometimes-uninitialized]

        default:

        ^~~~~~~

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:200:9:
note: uninitialized use occurs here

        return ts;

               ^~

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:180:2:
note: variable 'ts' is declared here

        enum dpia_set_config_ts ts;

        ^

1 error generated.

Fix it.
Reported-by: NMike Lothian <mike@fireburn.co.uk>
Signed-off-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The variable result is being initialized with a value that is never
read, it is being updated immediately afterwards in both branches
of an if statement. The assignment is redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
1. Remove unnecessary dummy interrupt source for USB4 HPD & HPD RX
2. Adjust parameter for DPCD writing of link training process of DPIA link
3. Adjust specific AUX defer delay for DPIA link
Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Additional debug flags that can be useful for testing USB4 DP
link training.

Add flags:
- 0x2 : Forces USB4 DP link to non-LTTPR mode
- 0x4 : Extends status read intervals to about 60s.
Reviewed-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DIB_BE_CNTL<i>.DIG_HPD_SELECT selects the HPD block being used
by the display endpoint assigned to DIG<i>. In the case of USB4
display endpoints, no physical HPD block is assigned.

[How]
Setting DIB_BE_CNTL<i>.DIG_HPD_SELECT to 5 indicates that no HPD
is assigned to a display endpoint. Firmware decrements the
HPD_SELECT value by 1 before writing it to the register.
Reviewed-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
To process SET_CONFIG transactions with DMUB using inbox1 and
outbox1 mail boxes.

[How]
1) DMUB posts SET_CONFIG reply as an Outbox1 message of type
   DMUB_OUT_CMD__SET_CONFIG_REPLY.
2) The dmub async to sync mechanism for AUX is modified to accommodate
   SET_CONFIG commands for both command issue and reply code paths.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJude Shih <shenshih@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
To add support for dpia debug options.
Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We requires information from DPCD in order to identify USB4 DP
tunneling targets.

[How]
Add USB4 DP tunneling fields to DPCD struct and populate these fields
during sink detection.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
To process SET_CONFIG transactions with DMUB using inbox1 and
outbox1 mail boxes.

[How]
1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to
   issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async().
   DMUB processes the command with DPIA sends reply back immediately or
   in an outbox1 message triggering an outbox1 interrupt to driver.
2) DMUB posts SET_CONFIG reply as an Outbox1 message of type
   DMUB_OUT_CMD__SET_CONFIG_REPLY.
3) The dmub async to sync mechanism for AUX is modified to accommodate
   SET_CONFIG commands for both command issue and reply code paths.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Clear training pattern sequence for hop in display path once clock
recovery and equalization phases of DP tunnel link training completed.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Equalisation is the mandatory second phase of DisplayPort link training
over a USB4 DP tunnel.

[How]
Implement equalisation phase for DP tunneled over USB4 in DPIA
training module.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Clock recovery is the mandatory first phase of DP link training.

[How]
- Implement clock recovery phase in DPIA training module.
- Add helper functions for building SET_CONFIG messages.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Training settings need to be applied to DPIA link at start of each
training loop. Note: FEC readiness should be configured before link
training while FEC enablement should be configured once training is
complete.

[How]
- Implement DPIA link configuration function.
- Account for dynamically assigned link encoders during link
configuration.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Training of DPIA link differs enough from that of conventional
DP link to warrant a separate implementation.

[How]
- Implement top-level of DPIA training loop.
- Make functions shared between DP and DPIA link training "public".
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Conventional links are trained with fallback during sink detection.
Have DPIA links trained with fallback too.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why & how]
Driver does not need to train the first hop.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why & how]
1. Add stub for getting tunneling device data
2. Add check for phy_repeater_cnt < 0xff to LTTPR check
3. Add two more bits of information to DPIA links
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why & how]
Add stub for DPIA link training and define new DPIA DMUB commands
to support it.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why & how]
We will need a way to distinguish physically connected
links and DPIA endpoints.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
To add support for HPD & HPD RX interrupt handling for USB4 DPIA in
YELLOW_CARP_B0. USB4 DPIA HPD & HPD RX interrupts are issued from DMUB to
driver as a outbox1 message.

[HOW]
1) Created get_link_index_from_dpia_port_index() to retrieve link index
   from dpia port index for HPD & HPD RX dmub notifications.
2) Added DMUB HPD & HPD RX handling in dmub_srv_stat_get_notification().
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
To enable dc links for USB4 DPIA ports and AUX command tunneling
for YELLOW_CARP_B0.

[HOW]
1) Created dc links for all USB4 DPIA ports in create_links().
   dc_link_construct() implementation is split for legacy DDC and DPIAs.
   As usb4 has no ddc, ddc->ddc_pin will be set to NULL for its dc link
   and this parameter will be used to identify the dc links as DPIA. The
   dc link for DPIA is further to be enhanced with implementation for link
   encoder and link initialization.
2) usb4_dpia_count in struct resource_pool will be initialized to 4 in
   dcn31_resource_construct() if the DCN is YELLOW_CARP_B0.
3) Enabled DMUB AUX via outbox for YELLOW_CARP_B0.
Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
USB4 endpoints are dynamically mapped. We create additional link
encoders for USB4 use when DC is created and destroy them when DC
is destructed
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <Wayne.Lin@amd.com>
Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
During DQE's promotion test, error appears in dmesg at boot
on dcn3.1;

[How]
Add NULL pointor check for the pointor to the amdgpu_dm_connector;
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NLeo (Hanghong) Ma <hanghong.ma@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Trying to enable multiple displays simultaneously exposed shortcomings
with the algorithm for dynamic link encoder assignment.

The main problems were:
- Assuming stream order remained constant across states would
sometimes lead to invalid DIG encoder assignment.
- Incorrect logic for deciding whether or not a DIG could support a
stream would also sometimes lead to invalid DIG encoder assignment.
- Changes in encoder assignment were wholesale while updating of the
pipe backend is incremental. This would lead to the hardware state
not matching the software state even with valid encoder assignments.

[How]

The following changes fix the identified problems.
- Use stream pointer rather than stream index to track streams across
states.
- Fix DIG compatibility check by examining the link signal type
rather than the stream signal type.
- Modify assignment algorithm to make incremental updates so software
and hardware states remain coherent.

Additionally:
- Add assertions and an encoder assignment validation
function link_enc_cfg_validate() to detect potential problems with
encoder assignment closer to their root cause.
- Reduce the frequency with which the assignment algorithm is
executed. It should not be necessary for fast state validation.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
The codes to blank all dp display have been called many times,
so add a helper in dc_link to make it more concise.
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NLeo (Hanghong) Ma <hanghong.ma@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following fixes:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection of 4 lane for DPALT
- Fix dcn3 failure due to dmcbu_abm not created
- Limit display scaling to up to 4k for DCN 3.1
- Add helper for blanking all dp displays
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers

[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NHansen <Hansen.Dsouza@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
The existing limit was mistakenly bigger than 4k for DCN 3.1
Reviewed-by: NZhan Liu <Zhan.Liu@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NNikola Cornij <nikola.cornij@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Added root clock optimization debug flags for future debugging.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NJake Wang <haonan.wang2@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Current FPU code for DCN2x is located under dml/dcn2x.
This is not aligned with DC's general source tree
structure.

[How]
Move FPU code for DCN2x to dml/dcn20.
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Overriding link setting inside override_training_settings
result in fallback link settings being ignored. This can
potentially cause link training to always fail and consequently
result in an infinite loop of link training to occur in
dp_verify_link_cap during detection.

[How]
Since preferred link settings are already considered inside
decide_link_settings, skip the check in override_training_settings
to avoid infinite link training loops.
Reviewed-by: NWenjing Liu <wenjing.liu@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No need for a separate kconfig option at this point.
Reviewed-by: NZhan Liu <zhan.liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
For some reason we're defining DP 2.0 definitions inside our
driver. Now that patches to introduce relevant definitions
are slated to be merged into drm-next this is causing conflicts.

In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
        ^
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
        ^
1 error generated.

[How]
Guard all display driver defines with #ifndef for now. Once we pull
in the new definitions into amd-staging-drm-next we will follow
up and drop definitions from our driver and provide follow-up
header updates for any addition DP 2.0 definitions required
by our driver.

We also ensure drm_dp_helper.h is included before dc_dp_types.h.

v3: Ensure drm_dp_helper.h is included before dc_dp_types.h

v2: Add one missing endif
Reviewed-by: NManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NFangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
add display related cyan_skillfish files in.

makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.

v2: squash in clang fixes from Harry, Nathan
v3: squash in missing CONFIG_DRM_AMD_DC check (Alex)
Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Signed-off-by: NZhan Liu <zhan.liu@amd.com>
Reviewed-by: NCharlene Liu <charlene.liu@amd.com>
Acked-by: NJun Lei <jun.lei@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The two AMD drivers have their own custom offsetof() implementation
that now triggers a warning with recent versions of clang:

drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer subtraction with a null pointer has undefined behavior [-Werror,-Wnull-pointer-subtraction]

Change all the instances to use the normal offsetof() provided
by the kernel that does not have this problem.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Recently debugging efforts have involved setting/checking the
X.Y value used during payload allocation. Current output for
Y was calculated with incorrect bitshift. Y value is also not
human readable.

[How]
Refactor logging into separate function. Fix Y calculation error
and format output to be human readable.
Reviewed-by: NWenjing Liu <wenjing.liu@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why/How]
Theoretically rare corner case where ceil(Y) results in rounding
up to an integer. If this happens, the 1 should be carried over to
the X value.
Reviewed-by: NWenjing Liu <wenjing.liu@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
There is a chance verified link cap can be greater than max link cap.
This causes software hang because we cannot power up PHY with link rate
that cannot handle.
The change is to guard verfieid link cap from becoming larger than max link cap
our PHy can support.
Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>