- 06 3月, 2015 2 次提交
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由 Robert ABEL 提交于
This patch adds support for spawning buses as children of the GPMC. Signed-off-by: NRobert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Robert ABEL 提交于
OMAP2+ GPMC driver undefines DEBUG, which makes it unnecessarily hard to turn DEBUG on. Remove the offending lines. Signed-off-by: NRobert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
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- 25 2月, 2015 2 次提交
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由 Semen Protsenko 提交于
Fix sparse warning: warning: symbol 'gpmc_cs_get_name' was not declared. Should it be static? Signed-off-by: NSemen Protsenko <semen.protsenko@globallogic.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Semen Protsenko 提交于
Some GPMC_CONFIG7 register bits marked as "RESERVED", means they shouldn't be overwritten. A typical approach to handle such bits called "Read-Modify-Write". Writing procedure used in gpmc_cs_set_memconf() utilizes RMW technique, but implemented incorrectly. Due to obvious typo in code read register value is being rewritten by another value, which leads to loss of read RESERVED bits. This patch fixes this. While at it, replace magic numbers with named constants to improve code readability. Signed-off-by: NSemen Protsenko <semen.protsenko@globallogic.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
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- 30 1月, 2015 1 次提交
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由 Scott Wood 提交于
T1040 has a different version of corenet-cf, despite being incorrectly labelled with a fsl,corenet2-cf compatible. The t1040 version of corenet-cf has a version register that can be read to distinguish. The t4240/b4860 version officially does not, but testing shows that it does and has a different value, so use that. If somehow this ends up not being reliable and we treat a t4240/b4860 as a t1040 (the reverse should not happen, as t1040's version register is official), currently the worst that should happen is writing to reserved bits to enable events that don't exist. The changes to the t1040 version of corenet-cf that this driver cares about are the addition of two new error events. There are also changes to the format of cecar2, which is printed, but not interpreted, by this driver. Signed-off-by: NScott Wood <scottwood@freescale.com>
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- 04 12月, 2014 1 次提交
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由 Thierry Reding 提交于
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: NJoerg Roedel <jroedel@suse.de> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 29 11月, 2014 1 次提交
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由 Tony Lindgren 提交于
Just move to drivers as further clean-up can now happen there finally. Let's also add Roger and me to the MAINTAINERS so we get notified for any patches related to GPMC. Cc: Arnd Bergmann <arnd@arndb.de> Acked-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 06 11月, 2014 1 次提交
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由 Aaron Sierra 提交于
Freescale's QorIQ T Series processors support 8 IFC chip selects within a memory map backward compatible with previous P Series processors which supported only 4 chip selects. Signed-off-by: NAaron Sierra <asierra@xes-inc.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 20 10月, 2014 1 次提交
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由 Wolfram Sang 提交于
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 30 7月, 2014 1 次提交
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由 Scott Wood 提交于
The CoreNet Coherency Fabric is part of the memory subsystem on some Freescale QorIQ chips. It can report coherency violations (e.g. due to misusing memory that is mapped noncoherent) as well as transactions that do not hit any local access window, or which hit a local access window with an invalid target ID. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NBharat Bhushan <bharat.bhushan@freescale.com>
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- 15 7月, 2014 1 次提交
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由 Alexandre Belloni 提交于
Atmel SoCs have one or multiple RAM controllers that need one or multiple clocks to run. This driver handle those clocks. Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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- 29 4月, 2014 5 次提交
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由 Thomas Petazzoni 提交于
Currently, the mvebu-devbus Device Tree binding makes defining the timing parameters mandatory. However, in practice, when converting Orion5x platforms to the Device Tree, we may not necessarily have easy access to the hardware platforms to fetch those values which were not defined in old-style board files: all these platforms rely on the bootloader setting the timing parameters correctly. In order to facilitate the migration to the Device Tree of this platform, this commit relaxes the mvebu-devbus Device Tree binding by introducing a 'devbus,keep-config' boolean property, which, if defined, will ignore all timing parameters passed in the Device Tree, and simply rely on the timing values already defined by the bootloader. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-10-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
This commit adds support for the Orion5x family of Marvell processors into the mvebu-devbus driver. It differs from the already supported Armada 370/XP by: * Having a single register (instead of two) for doing all the timing configuration. * Having a few less timing configuration parameters. For this reason, a separate compatible string "marvell,orion-devbus" is introduced. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-9-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the registers. Therefore, in preparation to the introduction of Orion5x support, we separate into two functions the code that 1/ retrieves the timing parameters from the Device Tree and 2/ applies those timings parameters into the hardware registers. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-8-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
As noted by Sebastian Hesselbarth, the definitions in mvebu-devbus.c are not bit definition, but rather shift values, so a _SHIFT prefix would make more sense. This commit therefore replaces the *_BIT definitions by *_SHIFT definitions. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-7-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-6-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 17 4月, 2014 1 次提交
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由 Thomas Petazzoni 提交于
According to the Armada 370 and Armada XP datasheets, the part of the Device Bus register that configure the bus width should contain 0 for a 8 bits bus width, and 1 for a 16 bits bus width (other values are unsupported/reserved). However, the current conversion done in the driver to convert from a bus width in bits to the value expected by the register leads to setting the register to 1 for a 8 bits bus, and 2 for a 16 bits bus. This mistake was compensated by a mistake in the existing Device Tree files for Armada 370/XP platforms: they were declaring a 8 bits bus width, while the hardware in fact uses a 16 bits bus width. This commit fixes that by adjusting the conversion logic. This patch fixes a bug that was introduced in 3edad321 ('drivers: memory: Introduce Marvell EBU Device Bus driver'), which was merged in v3.11. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397489361-5833-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 3edad321 ('drivers: memory: Introduce Marvell EBU Device Bus driver') Cc: stable@vger.kernel.org # v3.11+ Acked-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 01 3月, 2014 2 次提交
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由 Ivan Khoronzhuk 提交于
Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Paul Gortmaker 提交于
commit d2ae2e20 ("driver/memory:Move Freescale IFC driver to a common driver") introduces this build regression into the mpc85xx_defconfig: drivers/built-in.o: In function `fsl_ifc_nand_remove': drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `match_bank': drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to `convert_ifc_address' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' make: *** [vmlinux] Error 1 This happens because there is nothing to descend us into the drivers/memory directory in the mpc85xx_defconfig. It wasn't selecting CONFIG_MEMORY. So we never built drivers/memory/fsl_ifc.o and so we have nothing to link the above symbols against. Since the goal of the original commit was to relocate the driver to an arch independent location, it only makes sense to relocate the Kconfig setting there as well. But that alone won't fix the build failure; for that we ensure whoever selects FSL_IFC also selects MEMORY. Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 19 2月, 2014 1 次提交
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由 Prabhakar Kushwaha 提交于
Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/memory and fix the header file includes. Also remove module_platform_driver() and instead call platform_driver_register() from subsys_initcall() to make sure this module has been loaded before MTD partition parsing starts. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 16 8月, 2013 1 次提交
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由 Julia Lawall 提交于
Remove unneeded error handling on the result of a call to platform_get_resource when the value is passed to devm_ioremap_resource. A simplified version of the semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression pdev,res,n,e,e1; expression ret != 0; identifier l; @@ - res = platform_get_resource(pdev, IORESOURCE_MEM, n); ... when != res - if (res == NULL) { ... \(goto l;\|return ret;\) } ... when != res + res = platform_get_resource(pdev, IORESOURCE_MEM, n); e = devm_ioremap_resource(e1, res); // </smpl> Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 13 8月, 2013 1 次提交
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由 Ezequiel Garcia 提交于
This variable is not being used anywhere and it's only forgotten garbage that should have been removed in the previous commit: commit 9b6e4c0a Author: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Date: Fri Jul 26 10:17:38 2013 -0300 memory: mvebu-devbus: Remove address decoding window workaround Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 06 8月, 2013 1 次提交
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由 Ezequiel Garcia 提交于
Now that mbus device tree binding has been introduced, remove the address decoding window management from this driver. A suitable 'ranges' entry should be added to the devbus-compatible node in the device tree, as described by the mbus binding documentation. Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 18 6月, 2013 2 次提交
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由 Tuomas Tynkkynen 提交于
In Tegra30 any memory controller interrupt would cause an infinite loop in the IRQ handler. Additionally, a garbage pointer was used to read the MC status registers, which causes wrong values to be printed if a MC error occurred. Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@gmail.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Tuomas Tynkkynen 提交于
In Tegra20 any memory controller interrupt would cause an infinite loop in the IRQ handler. Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@gmail.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 22 5月, 2013 1 次提交
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由 Ezequiel Garcia 提交于
Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 18 5月, 2013 1 次提交
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由 Wolfram Sang 提交于
devm_ioremap_resource does sanity checks on the given resource. No need to duplicate this in the driver. Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 26 3月, 2013 8 次提交
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由 Lokesh Vutla 提交于
of_get_property returns value in Big Endian format. Before using this value it should be converted to little endian using be32_to_cpup(). Custom configs of emif are read from dt using of_get_property, but these are not converted to litte endian format. Correcting the same here. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Grygorii Strashko 提交于
ERRATA DESCRIPTION : The EMIF supports power-down state for low power. The EMIF automatically puts the SDRAM into power-down after the memory is not accessed for a defined number of cycles and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4. As the EMIF supports automatic output impedance calibration, a ZQ calibration long command is issued every time it exits active power-down and precharge power-down modes. The EMIF waits and blocks any other command during this calibration. The EMIF does not allow selective disabling of ZQ calibration upon exit of power-down mode. Due to very short periods of power-down cycles, ZQ calibration overhead creates bandwidth issues and increases overall system power consumption. On the other hand, issuing ZQ calibration long commands when exiting self-refresh is still required. WORKAROUND : Because there is no power consumption benefit of the power-down due to the calibration and there is a performance risk, the guideline is to not allow power-down state and, therefore, to not have set the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4. This is applicable only for EMIF4D IP used in OMAP4 Soc's. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NVitaly Chernooky <vitaly.chernooky@ti.com> Signed-off-by: NOleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Oleksandr Dmytryshyn 提交于
The issue was that only the first timings table was added to the emif platform data at the emif driver registration. All other timings tables was filled with zeros. Now all emif timings table are added to the platform data. Signed-off-by: NOleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Nishanth Menon 提交于
Some machine or kernel variants might have missed implementation of power off handlers. We DONOT want to let the system be in "out of spec" state in this condition. So, WARN and attempt a machine restart in the hopes of clearing the out-of-spec temperature condition. NOTE: This is not the safest option, but safer than leaving the system in unstable conditions. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Nishanth Menon 提交于
As per JESD209-2E specification for LPDDR2, http://www.jedec.org/standards-documents/results/jesd209-2E Table 73, LPDDR2 memories come in two flavors - Standard and Extended. The Standard types can operate from -25C to +85C However, beyond that and upto +105C can only be supported by Extended types. Unfortunately, it seems there is no info in MR0(device info) or MR[1,2](device feature) for run time detection of this capability as far as seen on the spec. Hence, we provide a custom_config flag to be populated by platforms which have these "extended" type memories. For the "Standard" memories, we need to consider MR4 notifications of temperature triggers >85C as equivalent to thermal shutdown events (equivalent to Spec specified thermal shutdown events for "extended" parts). Reported-by: NRichard Woodruff <r-woodruff2@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Nishanth Menon 提交于
In case the custom timings provide values which overflow the maximum possible field value, warn and use maximum permissible value. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Ambresh K 提交于
Program the power management shadow register on freq update Else the concept of threshold frequencies dont really matter as the system always uses the performance mode timing for LP which is programmed in at init time. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NAmbresh K <ambresh@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Lokesh Vutla 提交于
The driver tries to round up the specified timeout cycles to the next power of 2 value. This should be done defore updating timeout variable. Correcting this here. Reported-by: NNishanth Menon <nm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 16 3月, 2013 3 次提交
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由 Hiroshi Doyu 提交于
Make this depend on CONFIG_PM. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Fabio Porcedda 提交于
This patch converts the drivers to use the module_platform_driver_probe() macro which makes the code smaller and a bit simpler. Signed-off-by: NFabio Porcedda <fabio.porcedda@gmail.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Aneesh V <aneesh@ti.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Hiroshi Doyu 提交于
Make this depend on CONFIG_PM. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 23 1月, 2013 1 次提交
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由 Thierry Reding 提交于
Convert all uses of devm_request_and_ioremap() to the newly introduced devm_ioremap_resource() which provides more consistent error handling. devm_ioremap_resource() provides its own error messages so all explicit error messages can be removed from the failure code paths. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 04 1月, 2013 1 次提交
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由 Greg Kroah-Hartman 提交于
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, and __devinitconst, from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Hiroshi DOYU <hdoyu@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Axel Lin <axel.lin@gmail.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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