提交 · b0854514537e4e2f0a599ca05d18fe95dcd3ee42 · openeuler / Kernel

24 11月, 2014 40 次提交

clocksource: mips-gic: Move gic_frequency to clocksource driver · b0854514

由 Andrew Bresticker 提交于 10月 20, 2014

There's no reason for gic_frequency to be global any more and it
certainly doesn't belong in the GIC irqchip driver, so move it to
the GIC clocksource driver.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8137/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

b0854514

clocksource: mips-gic: Staticize local symbols · 5fee56e0

由 Andrew Bresticker 提交于 10月 20, 2014

There are a number of variables and functions which are unnecessarily
global.  Mark them static.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8135/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

5fee56e0

clocksource: mips-gic: Combine with GIC clockevent driver · a331ce63

由 Andrew Bresticker 提交于 10月 20, 2014

Combine the GIC clocksource driver with the GIC clockevent driver from
arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate
Kconfig symbol.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8132/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

a331ce63

MIPS: Move GIC clocksource driver to drivers/clocksource/ · fa5635a2

由 Andrew Bresticker 提交于 10月 20, 2014

Move the GIC clocksource driver to drivers/clocksource/mips-gic-timer.c.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8133/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

fa5635a2

irqchip: mips-gic: Use GIC_SH_WEDGE_{SET,CLR} macros · 53a7bc81

由 Andrew Bresticker 提交于 10月 20, 2014

Use the GIC_SH_WEDGE_{SET,CLR} macros provided by mips-gic.h.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8134/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

53a7bc81

irqchip: mips-gic: Remove gic_{pending,itrmask}_regs · 8f5ee79c

由 Andrew Bresticker 提交于 10月 20, 2014

There's no reason for the pending and masked interrupt bitmasks
to be global.  Just declare them on the stack in gic_get_int()
since they only consume (256*2)/8 = 64 bytes.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8131/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

8f5ee79c

irqchip: mips-gic: Clean up #includes · fb8f7be1

由 Andrew Bresticker 提交于 10月 20, 2014

Sort the #includes and remove those which are unnecessary.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8130/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

fb8f7be1

irqchip: mips-gic: Clean up header file · 824f3f7f

由 Andrew Bresticker 提交于 10月 20, 2014

Remove duplicate #defines and unnecessary #includes, fix parenthesization,
and re-order register definitions in ascending order.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8128/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

824f3f7f

MAINTAINERS: Add entry for bcm63xx/bcm33xx UDC gadget driver · 7110e227

由 Kevin Cernekee 提交于 10月 20, 2014

This hardware shows up on the newly-supported BCM3384 cable chip, as well
as several old BCM63xx DSL chips.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8172/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

7110e227

MAINTAINERS: Add entry for BCM33xx cable chips · a2f6734c

由 Kevin Cernekee 提交于 10月 20, 2014

Add myself as a maintainer for the new BCM3384 board support code.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8171/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

a2f6734c

MIPS: bcm3384: Initial commit of bcm3384 platform support · d666cd02

由 Kevin Cernekee 提交于 10月 20, 2014

This supports SMP Linux running on the BCM3384 Zephyr (BMIPS5000)
application processor, with fully functional UART and USB 1.1/2.0.
Device Tree is used to configure the following items:

 - All peripherals
 - Early console base address
 - SMP or UP mode
 - MIPS counter frequency
 - Memory size / regions
 - DMA offset
 - Kernel command line

The DT-enabled bootloader and build instructions are posted at
https://github.com/Broadcom/aeolusSigned-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8170/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

d666cd02

Documentation: DT: Add "mti" vendor prefix · ab81ce62

由 Kevin Cernekee 提交于 10月 20, 2014

We have a bunch of platforms using "mti,cpu-interrupt-controller" but
the "mti" prefix isn't documented.  Fix this.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8169/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

ab81ce62

Documentation: DT: Add entries for BCM3384 and its peripherals · 846deace

由 Kevin Cernekee 提交于 10月 20, 2014

This covers the new "brcm,*" devices added in the upcoming bcm3384 commit.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8168/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

846deace

MIPS: Create a helper function for DT setup · 84988c06

由 Kevin Cernekee 提交于 10月 20, 2014

A couple of platforms register two buses and call of_platform_populate().
Move this into a common function to reduce duplication.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8167/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

84988c06

MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind) · 68e6a783

由 Kevin Cernekee 提交于 10月 20, 2014

This is a dual core (quad thread) BMIPS5000.  It needs a little extra
code to boot the second core (CPU2/CPU3), but for now we can treat it the
same as a single core BMIPS5000.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8166/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

68e6a783

MIPS: BMIPS: Add special cache handling in c-r4k.c · d74b0172

由 Kevin Cernekee 提交于 10月 20, 2014

BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.

BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$.  But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure coherency.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8165/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

d74b0172

MIPS: BMIPS: Let each platform customize the CPU1 IRQ mask · d8010ceb

由 Kevin Cernekee 提交于 10月 20, 2014

On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1
input, generating spurious IRQs.  In this case we want the platform code
to be able to mask it off.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8163/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

d8010ceb

MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs · bbf2ba67

由 Kevin Cernekee 提交于 10月 20, 2014

BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2
line size.  If L1_CACHE_SHIFT is undersized, DMA buffers will not be
cacheline-aligned and terrible things will happen.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8164/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

bbf2ba67

MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizes · a7ef1ead

由 Kevin Cernekee 提交于 10月 20, 2014

CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c.  However,
it is currently hardwired to use an L1_SHIFT of 6 (64 bytes).  Move the
L1_SHIFT selection into the CPU or SoC section so that other SoCs can
select different values.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8162/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

a7ef1ead

MIPS: BMIPS: Explicitly configure reset vectors prior to secondary boot · 3677a283

由 Kevin Cernekee 提交于 10月 20, 2014

The secondary CPU's reset vector needs to be set to KSEG1 for a cold
boot (release from reset), or KSEG0 for a warm restart.  On a cold boot
KSEG0 may be unavailable (BMIPS4380), and on a warm restart KSEG1 may
be unavailable (XKS01 mode on 4380 or 5000).
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8161/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

3677a283

MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPU · 230b6ff5

由 Jon Fraser 提交于 10月 20, 2014

CPU interrupts need to be disabled on a cpu being taken down.
When a cpu is hot-plugged out of the system the following sequence occurs.

On the CPU where the hotplug sequence was initiated:
    cpu_down
        _cpu_down {
            __cpu_notify(CPU_DOWN_PREPARE
            __stop_machine(take_cpu_down
                wait for cpu to run disable code.
            __cpu_die
        }

On the CPU  being disabled:
    take_cpu_down
        __cpu_disable {
            mp_ops->cpu_disable
                bmips_cpu_disable
                    clear_c0_status(IE_IRQ5) (added)
            cpu_notify(CPU_DYING...
        }

Before the cpu_notifier is called with CPU_DYING, all interrupts on the
dying cpu must be disabled.  This guarantees that before tick_notify is
called with the CPU_DYING event and sets the clock device pointer to
NULL, there can not be any more clock interrupts.

When this wasn't done, an unfortunately-timed timer interrupt sometimes
caused hangs immediately prior to system suspend:

    Debug PM is not enabled. To enable partial suspend, rebuild kernel with CONFIG_PM_DEBUG
    Pass 1 out of 1,PM: Syncing filesystems ... mode=none, tp1=done.
    1, flags=5, cycle_tp=, sleep=
    Freezing user space processes ... (elapsed 0.01 seconds) done.
    Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
    PM: suspend of devices complete after 54.199 msecs
    PM: late suspend of devices complete after 0.172 msecs
    Disabling non-boot CPUs ...
    SMP: CPU1 is offline
    INFO: rcu_sched detected stalls on CPUs/tasks: { 3} (detected by 0, t=62537 jiffies)
    Call Trace:
    [<804baa78>] dump_stack+0x8/0x34
    [<8008a2d8>] __rcu_pending+0x4b8/0x55c
    [<8008adf4>] rcu_check_callbacks+0x78/0x180
    [<80037830>] update_process_times+0x40/0x6c
    [<80072fe4>] tick_sched_timer+0x74/0xe4
    [<80050180>] __run_hrtimer.clone.30+0x64/0x140
    [<80051150>] hrtimer_interrupt+0x19c/0x4bc
    [<8000cdb8>] c0_compare_interrupt+0x50/0x88
    [<80081b18>] handle_irq_event_percpu+0x5c/0x2f4
    [<80086490>] handle_percpu_irq+0x8c/0xc0
    [<800811b4>] generic_handle_irq+0x34/0x54
    [<800067dc>] do_IRQ+0x18/0x2c
    [<8000375c>] plat_irq_dispatch+0xd0/0x128
    [<80004a04>] ret_from_irq+0x0/0x4
    [<80004c40>] r4k_wait+0x20/0x40
    [<80006b6c>] cpu_idle+0x98/0xf0
    [<805d3988>] start_kernel+0x424/0x440
Signed-off-by: NJon Fraser <jfraser@broadcom.com>
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8160/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

230b6ff5

MIPS: BMIPS: Allow BMIPS3300 to utilize SMP ebase relocation code · fa010672

由 Jon Fraser 提交于 10月 20, 2014

BMIPS3300 processors do not have the hardware to support SMP, but with a
small tweak, the SMP ebase relocation code allows BMIPS3300-based
platforms to reuse the S2/S3 power management code from BMIPS4380-based
chips.  Normally this is as simple as adding one line to prom_init():

    board_ebase_setup = &bmips_ebase_setup;
Signed-off-by: NJon Fraser <jfraser@broadcom.com>
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8159/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

fa010672

MIPS: BMIPS: Introduce helper function to change the reset vector · fc455787

由 Kevin Cernekee 提交于 10月 20, 2014

This will need to be called from a few different places, and the logic
is starting to get a bit hairy (with the need for IPIs, CPU bug
workarounds, and hazards).
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8158/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

fc455787

MIPS: BMIPS: Align secondary boot sequence with latest firmware releases · bdb2e05c

由 Kevin Cernekee 提交于 10月 20, 2014

On some older BMIPS5200 (dual core / quad thread) platforms, the
PROM code set up CPU2/CPU3 so they would be started through an NMI
instead of through the ACTION register.  But this was incompatible with
some power management features that were later added, so the scheme was
changed so that Linux is fully responsible for booting CPU2/CPU3.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8157/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

bdb2e05c

clk: ls1x: Update relationship among all clocks · 3526f74f