1. 01 10月, 2015 3 次提交
    • S
      KVM: x86: Add EOI exit bitmap inference · b053b2ae
      Steve Rutherford 提交于
      In order to support a userspace IOAPIC interacting with an in kernel
      APIC, the EOI exit bitmaps need to be configurable.
      
      If the IOAPIC is in userspace (i.e. the irqchip has been split), the
      EOI exit bitmaps will be set whenever the GSI Routes are configured.
      In particular, for the low MSI routes are reservable for userspace
      IOAPICs. For these MSI routes, the EOI Exit bit corresponding to the
      destination vector of the route will be set for the destination VCPU.
      
      The intention is for the userspace IOAPICs to use the reservable MSI
      routes to inject interrupts into the guest.
      
      This is a slight abuse of the notion of an MSI Route, given that MSIs
      classically bypass the IOAPIC. It might be worthwhile to add an
      additional route type to improve clarity.
      
      Compile tested for Intel x86.
      Signed-off-by: NSteve Rutherford <srutherford@google.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      b053b2ae
    • S
      KVM: x86: Add KVM exit for IOAPIC EOIs · 7543a635
      Steve Rutherford 提交于
      Adds KVM_EXIT_IOAPIC_EOI which allows the kernel to EOI
      level-triggered IOAPIC interrupts.
      
      Uses a per VCPU exit bitmap to decide whether or not the IOAPIC needs
      to be informed (which is identical to the EOI_EXIT_BITMAP field used
      by modern x86 processors, but can also be used to elide kvm IOAPIC EOI
      exits on older processors).
      
      [Note: A prototype using ResampleFDs found that decoupling the EOI
      from the VCPU's thread made it possible for the VCPU to not see a
      recent EOI after reentering the guest. This does not match real
      hardware.]
      
      Compile tested for Intel x86.
      Signed-off-by: NSteve Rutherford <srutherford@google.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      7543a635
    • S
      KVM: x86: Split the APIC from the rest of IRQCHIP. · 49df6397
      Steve Rutherford 提交于
      First patch in a series which enables the relocation of the
      PIC/IOAPIC to userspace.
      
      Adds capability KVM_CAP_SPLIT_IRQCHIP;
      
      KVM_CAP_SPLIT_IRQCHIP enables the construction of LAPICs without the
      rest of the irqchip.
      
      Compile tested for x86.
      Signed-off-by: NSteve Rutherford <srutherford@google.com>
      Suggested-by: NAndrew Honig <ahonig@google.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      49df6397
  2. 23 7月, 2015 1 次提交
  3. 21 7月, 2015 4 次提交
  4. 05 6月, 2015 2 次提交
  5. 04 6月, 2015 1 次提交
  6. 07 5月, 2015 1 次提交
    • N
      KVM: x86: Support for disabling quirks · 90de4a18
      Nadav Amit 提交于
      Introducing KVM_CAP_DISABLE_QUIRKS for disabling x86 quirks that were previous
      created in order to overcome QEMU issues. Those issue were mostly result of
      invalid VM BIOS.  Currently there are two quirks that can be disabled:
      
      1. KVM_QUIRK_LINT0_REENABLED - LINT0 was enabled after boot
      2. KVM_QUIRK_CD_NW_CLEARED - CD and NW are cleared after boot
      
      These two issues are already resolved in recent releases of QEMU, and would
      therefore be disabled by QEMU.
      Signed-off-by: NNadav Amit <namit@cs.technion.ac.il>
      Message-Id: <1428879221-29996-1-git-send-email-namit@cs.technion.ac.il>
      [Report capability from KVM_CHECK_EXTENSION too. - Paolo]
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      90de4a18
  7. 21 4月, 2015 1 次提交
    • M
      KVM: PPC: Book3S HV: Add fast real-mode H_RANDOM implementation. · e928e9cb
      Michael Ellerman 提交于
      Some PowerNV systems include a hardware random-number generator.
      This HWRNG is present on POWER7+ and POWER8 chips and is capable of
      generating one 64-bit random number every microsecond.  The random
      numbers are produced by sampling a set of 64 unstable high-frequency
      oscillators and are almost completely entropic.
      
      PAPR defines an H_RANDOM hypercall which guests can use to obtain one
      64-bit random sample from the HWRNG.  This adds a real-mode
      implementation of the H_RANDOM hypercall.  This hypercall was
      implemented in real mode because the latency of reading the HWRNG is
      generally small compared to the latency of a guest exit and entry for
      all the threads in the same virtual core.
      
      Userspace can detect the presence of the HWRNG and the H_RANDOM
      implementation by querying the KVM_CAP_PPC_HWRNG capability.  The
      H_RANDOM hypercall implementation will only be invoked when the guest
      does an H_RANDOM hypercall if userspace first enables the in-kernel
      H_RANDOM implementation using the KVM_CAP_PPC_ENABLE_HCALL capability.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      e928e9cb
  8. 01 4月, 2015 2 次提交
  9. 28 3月, 2015 6 次提交
    • J
      MIPS: KVM: Wire up MSA capability · d952bd07
      James Hogan 提交于
      Now that the code is in place for KVM to support MIPS SIMD Architecutre
      (MSA) in MIPS guests, wire up the new KVM_CAP_MIPS_MSA capability.
      
      For backwards compatibility, the capability must be explicitly enabled
      in order to detect or make use of MSA from the guest.
      
      The capability is not supported if the hardware supports MSA vector
      partitioning, since the extra support cannot be tested yet and it
      extends the state that the userland program would have to save.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NPaolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      d952bd07
    • J
      MIPS: KVM: Expose MSA registers · ab86bd60
      James Hogan 提交于
      Add KVM register numbers for the MIPS SIMD Architecture (MSA) registers,
      and implement access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG
      ioctls when the MSA capability is enabled (exposed in a later patch) and
      present in the guest according to its Config3.MSAP bit.
      
      The MSA vector registers use the same register numbers as the FPU
      registers except with a different size (128bits). Since MSA depends on
      Status.FR=1, these registers are inaccessible when Status.FR=0. These
      registers are returned as a single native endian 128bit value, rather
      than least significant half first with each 64-bit half native endian as
      the kernel uses internally.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      ab86bd60
    • J
      MIPS: KVM: Wire up FPU capability · 5fafd874
      James Hogan 提交于
      Now that the code is in place for KVM to support FPU in MIPS KVM guests,
      wire up the new KVM_CAP_MIPS_FPU capability.
      
      For backwards compatibility, the capability must be explicitly enabled
      in order to detect or make use of the FPU from the guest.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      5fafd874
    • J
      MIPS: KVM: Expose FPU registers · 379245cd
      James Hogan 提交于
      Add KVM register numbers for the MIPS FPU registers, and implement
      access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG ioctls when
      the FPU capability is enabled (exposed in a later patch) and present in
      the guest according to its Config1.FP bit.
      
      The registers are accessible in the current mode of the guest, with each
      sized access showing what the guest would see with an equivalent access,
      and like the architecture they may become UNPREDICTABLE if the FR mode
      is changed. When FR=0, odd doubles are inaccessible as they do not exist
      in that mode.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NPaolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      379245cd
    • J
      MIPS: KVM: Add Config4/5 and writing of Config registers · c771607a
      James Hogan 提交于
      Add Config4 and Config5 co-processor 0 registers, and add capability to
      write the Config1, Config3, Config4, and Config5 registers using the KVM
      API.
      
      Only supported bits can be written, to minimise the chances of the guest
      being given a configuration from e.g. QEMU that is inconsistent with
      that being emulated, and as such the handling is in trap_emul.c as it
      may need to be different for VZ. Currently the only modification
      permitted is to make Config4 and Config5 exist via the M bits, but other
      bits will be added for FPU and MSA support in future patches.
      
      Care should be taken by userland not to change bits without fully
      handling the possible extra state that may then exist and which the
      guest may begin to use and depend on.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      c771607a
    • J
      MIPS: KVM: Implement PRid CP0 register access · 1068eaaf
      James Hogan 提交于
      Implement access to the guest Processor Identification CP0 register
      using the KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls. This allows the
      owning process to modify and read back the value that is exposed to the
      guest in this register.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1068eaaf
  10. 17 3月, 2015 3 次提交
  11. 14 3月, 2015 1 次提交
  12. 12 3月, 2015 1 次提交
    • E
      KVM: arm/arm64: add irqfd support · 174178fe
      Eric Auger 提交于
      This patch enables irqfd on arm/arm64.
      
      Both irqfd and resamplefd are supported. Injection is implemented
      in vgic.c without routing.
      
      This patch enables CONFIG_HAVE_KVM_EVENTFD and CONFIG_HAVE_KVM_IRQFD.
      
      KVM_CAP_IRQFD is now advertised. KVM_CAP_IRQFD_RESAMPLE capability
      automatically is advertised as soon as CONFIG_HAVE_KVM_IRQFD is set.
      
      Irqfd injection is restricted to SPI. The rationale behind not
      supporting PPI irqfd injection is that any device using a PPI would
      be a private-to-the-CPU device (timer for instance), so its state
      would have to be context-switched along with the VCPU and would
      require in-kernel wiring anyhow. It is not a relevant use case for
      irqfds.
      Signed-off-by: NEric Auger <eric.auger@linaro.org>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org>
      174178fe
  13. 06 3月, 2015 1 次提交
    • E
      KVM: s390: Allocate and save/restore vector registers · 68c55750
      Eric Farman 提交于
      Define and allocate space for both the host and guest views of
      the vector registers for a given vcpu.  The 32 vector registers
      occupy 128 bits each (512 bytes total), but architecturally are
      paired with 512 additional bytes of reserved space for future
      expansion.
      
      The kvm_sync_regs structs containing the registers are union'ed
      with 1024 bytes of padding in the common kvm_run struct.  The
      addition of 1024 bytes of new register information clearly exceeds
      the existing union, so an expansion of that padding is required.
      
      When changing environments, we need to appropriately save and
      restore the vector registers viewed by both the host and guest,
      into and out of the sync_regs space.
      
      The floating point registers overlay the upper half of vector
      registers 0-15, so there's a bit of data duplication here that
      needs to be carefully avoided.
      Signed-off-by: NEric Farman <farman@linux.vnet.ibm.com>
      Reviewed-by: NThomas Huth <thuth@linux.vnet.ibm.com>
      Acked-by: NChristian Borntraeger <borntraeger@de.ibm.com>
      Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com>
      68c55750
  14. 23 1月, 2015 2 次提交
  15. 21 1月, 2015 1 次提交
  16. 13 12月, 2014 3 次提交
  17. 20 11月, 2014 1 次提交
  18. 03 11月, 2014 1 次提交
    • M
      kvm: drop unsupported capabilities, fix documentation · 7f05db6a
      Michael S. Tsirkin 提交于
      No kernel ever reported KVM_CAP_DEVICE_MSIX, KVM_CAP_DEVICE_MSI,
      KVM_CAP_DEVICE_ASSIGNMENT, KVM_CAP_DEVICE_DEASSIGNMENT.
      
      This makes the documentation wrong, and no application ever
      written to use these capabilities has a chance to work correctly.
      The only way to detect support is to try, and test errno for ENOTTY.
      That's unfortunate, but we can't fix the past.
      
      Document the actual semantics, and drop the definitions from
      the exported header to make it easier for application
      developers to note and fix the bug.
      Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      7f05db6a
  19. 22 9月, 2014 1 次提交
  20. 10 9月, 2014 2 次提交
  21. 25 8月, 2014 1 次提交
  22. 29 7月, 2014 1 次提交