Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-6-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

A plenty of DP PHY registers are common between V3 and V4. To simplify
V4 code, rename all common registers.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-5-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

In preparation to adding support for V4 DP PHY move DP functions to
callbacks at struct qmp_phy_cfg.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-4-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add compatible for SM8250 in QMP USB3 DP PHY bindings.
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-3-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

The commit 724fabf5 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy
information") has support for DP part of USB3+DP combo PHYs. However
this change is not backwards compatible, placing additional requirements
onto qcom,sc7180-qmp-usb3-phy and qcom,sdm845-qmp-usb3-phy device nodes
(to include separate DP part, etc). However the aforementioned nodes do
not inclue DP part, they strictly follow the schema defined in the
qcom,qmp-phy.yaml file. Move those compatibles, leaving
qcom,qmp-usb3-dp-phy.yaml to describe only real "combo" USB3+DP device nodes.

Fixes: 724fabf5 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information")
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210331151614.3810197-2-dmitry.baryshkov@linaro.orgSigned-off-by: NVinod Koul <vkoul@kernel.org>

Configure 'p_standard_mode' only for DP/QSGMII as for other modes
it's not used as per the programming sequence. Add "continue" in the
else to prevent random value from being written to p_standard_mode.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210331131417.15596-1-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

This commit fixes the warning messages of make dt_binding_check from
newly added mediatek,mt8195-ufsphy in mediatek,ufs-phy.yaml
Signed-off-by: NSeiya Wang <seiya.wang@mediatek.com>
Acked-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210319023427.16711-9-seiya.wang@mediatek.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

The current driver is not handling the clock enable/disable operations
properly. The clocks need to be handled correctly by enabling or
disabling at appropriate places. This patch adds code to handle the
same.
Signed-off-by: NManish Narani <manish.narani@xilinx.com>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/1616588325-95602-1-git-send-email-manish.narani@xilinx.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

1. Change syntax from txt to yaml
2. Drop "Driver for" from the title
3. Drop "reg = <0x0>;" from example (noticed by dt_binding_check)
4. Specify license
Signed-off-by: NRafał Miłecki <rafal@milecki.pl>
Reviewed-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210329165056.31647-1-zajec5@gmail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

1. Convert from txt to yaml
2. Drop "Driver for" from the title
3. Document "#phy-cells"
4. Fix example node name (noticed by dt_binding_check)
5. Add #include to example (noticed by dt_binding_check)
6. Specify license
Signed-off-by: NRafał Miłecki <rafal@milecki.pl>
Reviewed-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210329165041.31574-1-zajec5@gmail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

The Microchip Sparx5 SerDes PHY is present only Microchip Sparx5 SoCs.
Hence add a dependency on ARCH_SPARX5, to prevent asking the user about
this driver when configuring a kernel without support for Sparx5 SoCs.

Fixes: 2ff8a1ee ("phy: Add Sparx5 ethernet serdes PHY driver")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210331081937.367408-1-geert+renesas@glider.beSigned-off-by: NVinod Koul <vkoul@kernel.org>

The Torrent spec specifies delay of 660.5us after phy_reset is
asserted by the controller. To be on the safe side provide a delay
of 5ms to 10ms in ->phy_on() callback where the SERDES is already
configured in bootloader.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210330110138.24356-6-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Since the reset controls obtained in
Torrent is exclusively used by the Torrent device, use
exclusive reset control request API calls.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Do not configure torrent SERDES if it's already configured.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-4-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change intended. Group reset APIs and clock APIs in
preparation for adding support to skip configuration if the SERDES
is already configured by bootloader.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210330110138.24356-3-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Serdes lanes might be shared between multiple cores in some usecases
and its not possible to lock PLLs for both the lanes independently
by the two cores. This requires a bootloader to configure both the
lanes at early boot time.

To handle this case, skip all configuration if any of the lanes has
already been enabled.
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210330110138.24356-2-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-14-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add #clock-cells binding to model Sierra as clock provider and include
clock IDs for PLL_CMNLC and PLL_CMNLC1.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210319124128.13308-12-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

commit 44d30d62 ("phy: cadence: Add driver for Sierra PHY") enabled
the clock in probe and failed to disable in remove callback. Add missing
clk_disable_unprepare() in cdns_sierra_phy_remove().

Fixes: 44d30d62 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210319124128.13308-11-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. In order to have a single header file for all
Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is
in preparation for adding Cadence Sierra SERDES specific macros.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Acked-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210319124128.13308-9-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-7-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-6-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

"serdes" node (child node of WIZ) can have sub-nodes for representing links
or it can have sub-nodes for representing the various clocks within the
serdes. Instead of trying to read "reg" from every child node used for
assigning "lane_phy_type", read only if the child node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnode.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20210319124128.13308-5-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-4-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Invoke wiz_init() before configuring anything else in Sierra/Torrent
(invoked as part of of_platform_device_create()). wiz_init() resets the
SERDES device and any configuration done in the probe() of
Sierra/Torrent will be lost. In order to prevent SERDES configuration
from getting reset, invoke wiz_init() immediately before invoking
of_platform_device_create().

Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Cc: <stable@vger.kernel.org> # v5.10
Link: https://lore.kernel.org/r/20210319124128.13308-3-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Commit 44d30d62 ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.

Fixes: 44d30d62 ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Cc: <stable@vger.kernel.org> # v5.4+
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Add hbr3_hbr2 voltage and premphasis swing table to support
HBR3 link rate.
Signed-off-by: NKuogee Hsieh <khsieh@codeaurora.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1615914761-12300-1-git-send-email-khsieh@codeaurora.org
Fixes: 52e013d0 ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy")
Signed-off-by: NVinod Koul <vkoul@kernel.org>

Fix the return value check typo which testing the wrong variable
in ingenic_usb_phy_probe().

Fixes: 31de313d ("PHY: Ingenic: Add USB PHY driver using generic PHY framework.")
Reported-by: NHulk Robot <hulkci@huawei.com>
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Acked-by: NPaul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210305034933.3240914-1-weiyongjun1@huawei.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Fix the return value check which testing the wrong variable
in mt7621_pci_phy_probe().

Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: NHulk Robot <hulkci@huawei.com>
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210305034931.3237558-1-weiyongjun1@huawei.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Merely enabling CONFIG_COMPILE_TEST should not enable additional code.
To fix this, restrict the automatic enabling of ARMADA375_USBCLUSTER_PHY
to MACH_ARMADA_375, and ask the user in case of compile-testing.

Fixes: eee47538 ("phy: add support for USB cluster on the Armada 375 SoC")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210208150252.424706-1-geert+renesas@glider.beSigned-off-by: NVinod Koul <vkoul@kernel.org>

In one of the error paths of the for_each_child_of_node() loop in
of_property_read_u32, add missing call to of_node_put().

Fix the following coccicheck warning:
./drivers/phy/ti/phy-j721e-wiz.c:786:1-23: WARNING: Function
"for_each_child_of_node" should have of_node_put() before return around
line 795.
Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1614244674-66556-1-git-send-email-yang.lee@linux.alibaba.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

When this was rewriten to get mainlined and start to
use 'linux/bitfield.h' headers, XTAL_MASK was wrong.
It must mask three bits but only two were used. Hence
properly fix it to make things work.

Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Update PCIe + USB register sequences for correct PLL1 clock configuration.
Also, update sequences for other USB configurations with dependent changes.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Update SGMII/QSGMII configuration specific to TI.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1614838096-32291-4-git-send-email-sjakhade@cadence.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

Configure MAC clock dividers required for QSGMII to be functional.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1614838096-32291-3-git-send-email-sjakhade@cadence.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

For PCIe + QSGMII configuration where QSGMII was using PLL1 and was
expecting 10GHz clock, configuration was giving 8GHz clock. Update
register sequences to get correct PLL1 configuration.

Also, update single link PCIe and single link SGMII/QSGMII configurations
with related changes.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.comSigned-off-by: NVinod Koul <vkoul@kernel.org>

cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_<p/m> can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.

This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.comSigned-off-by: NVinod Koul <vkoul@kernel.org>