1. 25 8月, 2017 1 次提交
  2. 10 8月, 2017 1 次提交
    • B
      ASoC: codecs: add const to snd_soc_codec_driver structures · a180ba45
      Bhumika Goyal 提交于
      Declare snd_soc_codec_driver structures as const as they are only passed
      as an argument to the function snd_soc_register_codec. This argument is
      of type const, so declare the structures with this property as const.
      In file codecs/sn95031.c, snd_soc_codec_driver structure is also used in
      a copy operation along with getting passed to snd_soc_register_codec.
      So, it can be made const too.
      Done using Coccinelle:
      
      @match disable optional_qualifier@
      identifier s;
      position p;
      @@
      static struct snd_soc_codec_driver s@p={...};
      
      @good1@
      identifier match.s;
      position p;
      @@
      snd_soc_register_codec(...,&s@p,...)
      
      @bad@
      identifier match.s;
      position p!={match.p,good1.p};
      @@
      s@p
      
      @depends on !bad disable optional_qualifier@
      identifier match.s;
      @@
      static
      +const
      struct snd_soc_codec_driver s={...};
      Signed-off-by: NBhumika Goyal <bhumirks@gmail.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      a180ba45
  3. 30 6月, 2017 1 次提交
  4. 29 6月, 2017 1 次提交
  5. 23 6月, 2017 3 次提交
    • J
      ASoC: nau8825: make crosstalk function optional · 2bda4288
      John Hsu 提交于
      Make crosstalk functoin optional.
      The jack detection can speed up without crosstalk detection.
      Let the decision of function usage to platform design.
      
      The patch helps the issue concern as follows:
      Google issue 35574278: Chell_headphone pop back from S3
      
      There is a concern as follows:
      cras getting blocked for 2 seconds (worst-case 3 seconds)
      As I understand, ChromeOS expects resume finishes in 1 seconds.
      Video/Audio playing after 3 seconds of resume seems against the spec.
      If we really have to make the choice I would choose pop noise instead
      of waiting for 3 seconds.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NJohn Hsu <supercraig0719@gmail.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      2bda4288
    • J
      ASoC: nau8825: fix jack type detection issue after resume · 8fe19795
      John Hsu 提交于
      Fix the issue that mic type detection error after resume.
      The microphone type detection procedure will recognize
      testing signal on JKSLV pin, but before the procedure,
      JKSLV already had supply voltage, that results in the failure.
      Therefore, the patch turns off the power and reset the jack type
      configuration before suspend. Then redo the jack detection
      procedure after resume.
      
      The patch help to fix the issue as follows:
      Google issue 37973093: CTIA/OMTP jack type detection failure after resume
      Reported Issue
      Chrome OS Version  :  ChromeOS R59-9460.13.0
      Type of hardware   :  DVT sample
      
      What steps will reproduce the problem?
      (1 Play a music
      (2 Insert a headphones
      (3 Close laptop lid 3 sec then open it
      What is the expected output?
      The music is normal in the headphones.
      What do you see instead?
      Singer voice in the music is not clear.
      
      How frequently does this problem reproduce?
      Always
      
      What is the impact to the user, and is there a workaround?
      If so, what is it?
      Re-insert the headset or close the laptop lid and
      then open it again can be repaired.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NJohn Hsu <supercraig0719@gmail.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      8fe19795
    • J
      ASoC: nau8825: default value for property · 403d2fef
      John Hsu 提交于
      Assign default value for codec private data when property not given.
      If without those default value and property, the codec will work
      abnormally.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NJohn Hsu <supercraig0719@gmail.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      403d2fef
  6. 17 2月, 2017 1 次提交
  7. 01 1月, 2017 2 次提交
  8. 06 12月, 2016 1 次提交
  9. 01 12月, 2016 1 次提交
    • J
      ASoC: nau8825: lock longer to avoid playback pop upon resume · 2263fddc
      John Hsu 提交于
      There is an issue about pop noise in NAU88L25 as follows.
      Issue 54078: Chell_headphone pop back from S3
      (1)Play directly to hw, bypassing CRAS:
      sox -b 16 -n -t alsa hw:0,0 synth sine 200 sine 200
      (2)Close lid or powerd_dbus_suspend, then press a key to resume.
      (3)no audio after resume
      (4)Audio will be back after close then reopen the pcm device.
      
      After verification, we find one defect is that semaphone lock is not
      long enough and expired. In this situation, the playback comes back
      early but pauses a while to wait for the crosstalk detection done.
      But the detection spends too much time and lock time is up. Therefore,
      the playback and jack detection sequence interfere to each other.
      That breaks sequence and makes noise. The driver extends the lock
      time for the issue.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      2263fddc
  10. 11 11月, 2016 3 次提交
    • J
      ASoC: nau8825: FLL parameters finetune · aee02c75
      John Hsu 提交于
      The driver fine-tune some parameters to improve FLL performance.
      Those items have description as follow.
      (1)ICTRL_LATCH: FLL DSP speed capability control
      When FLL running at high frequency with long decimal number, DSP needs
      to operate at high speed. FLL DSP can optimize between performance and
      power consumption by ICTRL_LATCH.(111 has highest power consumption.)
      The default setting can be used to reduce power.
      (2)CUTOFF500: loop filter cutoff frequency at 500Khz
      It will give the best FLL performance but highest power consumption
      to enable the cutoff frequency. FLL Loop Filter enable to reduce FLL
      output noise, especially,(DCO frequency)/(FLL input reference frequency)
      is not a integer.
      (3)GAIN_ERR: FLL gain error correction threshold setting
      The threshold is comparison between DCO and target frequency.
      The value 1111 has the most sensitive threshold, that is, 1111 can have
      the most accurate DCO to target frequency. However, the gain error setting
      conditionally and inversely depends on FLL input reference clock rate.
      Higher FLL reference input frequency can only set lower gain error, such
      as 0000 for input reference from MCLK=12.288Mhz. On the other side, if FLL
      reference input is from Frame Sync, 48KHz, higher error gain can apply
      such as 1111.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      aee02c75
    • J
      ASoC: nau8825: AD/DA over sampling rate configuration · d6d19745
      John Hsu 提交于
      Over Sampling Rate (OSR) is defined as CLK_ADC frequency divided by the
      audio sample rate (Fs).
      OSR = CLK_ADC / FS
      The available OSRs are 32, 64, 128 or 256. Note that the OSR and Fs
      values must be selected such that the maximum frequency of CLK_ADC
      is less than 6.144 MHz. It is recommended to match the relationship
      between OSR and clock SRC according to following Table.
      ADC_RATE: 00(OSR=32)  | CLK_ADC_SRC: 11(CODEC 1/8)
      ADC_RATE: 01(OSR=64)  | CLK_ADC_SRC: 10(CODEC1/4)
      ADC_RATE: 10(OSR=128) | CLK_ADC_SRC: 01(CODEC 1/2)
      ADC_RATE: 11(OSR=256) | CLK_ADC_SRC: 00(CODEC CLK)
      
      The over sampling rate about DAC follows the same rule with ADCs.
      The driver changes the OSR to 64 value when initiation for better FLL
      performance and applies the dynamic SRC change by different OSR.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      d6d19745
    • J
      ASoC: nau8825: Disable short Frame Sync detection logic · 93dfec75
      John Hsu 提交于
      If the short Frame Sync detection logic enabled, the logic will check the
      short frame sync threshold. If frame sync is less than the setting;
      for example, frame sync less than 252 MCLK, the short frame sync signal is
      flagged, digital filter temporary mute and skip that data.
      
      If the system was intended for sampling rate change which could create
      temporary short frame sync and not enough MIPS to run the digital filter.
      But the situation doesn't happen in ALSA architecure. Thus the Frame Sync
      is always stable, then no require to do the detection. Therefore,
      the dirver disables the function for better performance.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      93dfec75
  11. 14 9月, 2016 1 次提交
  12. 08 8月, 2016 1 次提交
  13. 05 8月, 2016 2 次提交
    • J
      ASoC: nau8825: fix static check error about semaphone control · 06746c67
      John Hsu 提交于
      The patch is to fix the static check error as the following.
      
      The patch commit b50455fa ("ASoC: nau8825: cross talk suppression
      measurement function") from Jun 7, 2016, leads to the following
      static checker warning:
      
      	sound/soc/codecs/nau8825.c:265 nau8825_sema_acquire()
      	warn: 'sem:&nau8825->xtalk_sem' is sometimes locked here and
      	sometimes unlocked.
      
      The semaphone acquire function has return value, and some callers
      can do error handling when lock fails.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      06746c67
    • J
      ASoC: nau8825: fix bug in playback when suspend · ca6ac305
      John Hsu 提交于
      In chromium, the following steps will make codec function fail.
      \1. plug in headphones, Play music
      \2. run "powerd_dbus_suspend"
      \3. resume from S3
      After resume, the jack detection will restart and make configuration
      for the headset. Meanwhile, the playback prepares and starts to work.
      The two sequences will conflict and make wrong register configuration.
      
      Originally, the driver adds protection for the case when it finds
      the playback is active. But the "powerd_dbus_suspend" command will
      close the pcm stream before suspend. Therefore, the driver can't
      detect the playback after resume, and the protection not works.
      For the issue, the driver raises protection every time after resume.
      The protection will release after jack detection and configuration
      completes, and then the playback just will goes on.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      ca6ac305
  14. 15 7月, 2016 2 次提交
  15. 14 6月, 2016 1 次提交
    • A
      ASoC: nau8825: mark pm functions __maybe_unused · 4983d325
      Arnd Bergmann 提交于
      The newly added nau8825_dai_is_active() function is only called from
      the PM logic that is build-time conditional in this driver, so we get
      a warning when CONFIG_PM is disabled:
      
      sound/soc/codecs/nau8825.c:229:13: error: 'nau8825_dai_is_active' defined but not used [-Werror=unused-function]
       static bool nau8825_dai_is_active(struct nau8825 *nau8825)
      
      By replacing the #ifdef around the functions with a __maybe_unused
      annotation, the code becomes more robust to this kind of problem
      and we no longer get the warning while also slightly improving
      readability.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Fixes: b50455fa ("ASoC: nau8825: cross talk suppression measurement function")
      Signed-off-by: NMark Brown <broonie@kernel.org>
      4983d325
  16. 13 6月, 2016 1 次提交
    • J
      ASoC: nau8825: cross talk suppression measurement function · b50455fa
      John Hsu 提交于
      The cross talk measurement function can reduce cross talk across the JKTIP
      HPL) and JKR1(HPR) outputs which measures the cross talk signal level to
      determine what is the cross talk reduction gain. This system works by
      sending a 23Hz -24dBV sine wave into the headset output DAC and through
      the PGA. The output of the PGA is then connected to an internal current
      sense which measures the attenuated 23Hz signal and passing the output to
      an ADC which converts the measurement to a binary code. With two separated
      measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
      can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
      
      Thus, the measurement function has four states to complete whole sequence.
      (1)Prepare state : Prepare the resource for detection and transfer to HPR
      IMM stat to make JKR1(HPR) impedance measure.
      (2)HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
      to HPL IMM state to make JKTIP(HPL) impedance measure.
      (3)HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
      transfer to IMM state to determine suppression sidetone gain.
      (4)IMM state : Computes cross talk suppression sidetone gain with orignal
      and cross talk signal level. Apply this gain and then restore codec con-
      figuration. Then transfer to Done state for ending.
      
      In order to get the cross talk suppression sidetone gain, we need the
      function to compute log10 value and the result is round off to 3 decimal.
      This function takes reference to dvb-math. The source code locates as the
      following. "Linux/drivers/media/dvb-core/dvb_math.c"
      Then, the orignal and cross talk signal vlues need to be characterized.
      The sidetone value can be converted to decibel with the equation below.
      sidetone = 20 * log (original signal level / crosstalk signal level)
      
      Besides, the state machine for cross talk process needs interruptions to
      trigger worked. We have the RMS intrruption enabled with the internal VCO
      clock when headset connected. In the interrupt handler, the driver will
      judge the headset is high impedance or not. If yes, the cross talk supp-
      ression shouldn't apply and do nothing but relieve the protection raised
      before. Otherwise, apply the cross talk suppression in the headset and
      start the process.
      
      Because the process spends a lot of time, there is an resource race issue
      easily between the application and interruption. They will control codec
      power and clock concurrently. In one situaiton, the jack is inserted when
      playback, and then the application changes to headset device. The applica-
      tion prepares the playback and interrupt handler raises work for cross
      talk process together. For this case, the solution is that driver delays
      soc jack report until cross talk process completes. The mechanism can
      avoid application to do playback preparation before cross talk detection
      is still working.
      In another situaiton, the system suspends when playback. After resume, the
      system restarts playback, and meanwhile jack detection restarts. The play-
      back preparation and cross talk process triggered by interruptions happens
      concurrently. For the case, the driver provides the semaphone to syn-
      chronize the playback and interrupt handler. In order to avoid the play-
      back interfered by cross talk process, the driver make the playback prepa-
      ration halted until cross talk process finish. After codec resume, the
      driver finds the codec dai is active, and then the driver raises the pro-
      tection for cross talk function to avoid the playback recovers before
      cross talk process finish.
      
      The driver also provides cancel method to forcely cancel the cross talk
      task and restores the configuration to original status. Before the codec
      remove, ejection, or suspend, the driver is obliged to cancel the cross
      talk detection process. It can reduce the risk of failure when quickly and
      continually doing jack insertion and ejection.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      b50455fa
  17. 03 6月, 2016 1 次提交
  18. 01 6月, 2016 2 次提交
    • J
      ASoC: nau8825: non-clock jack detection for power saving at standby · 2ec30f60
      John Hsu 提交于
      The driver changes jack type detection interruption to non-clock archi-
      tecture for less 1mW power saving. The architecture is called manual mode
      jack detection. It has no hardware debounce, no jack type detection, but
      only detecting jack insertion. After jack insertion, the driver will
      switch to auto mode jack detection with internal clock which can detect
      microphone, jack type and do hardware debounce.
      
      The manual architecture has these main changes including codec initiation,
      interruption, clock control, and power management. When codec initiation
      or system resume, the clock is closed as jack insertion detection at man-
      ual mode, and bypass debounce circuit. These configurations move to resume
      setup function when setup bias level after resume.
      
      When jack insertion detection happens, the manual mode turns off and make
      configuration about jack type detection interruption at auto mode in auto
      irq setup function which can detect microphone and jack type. The inter-
      ruption will switch to manual mode again with clock free until jack ejec-
      tion happens.
      
      The system clock configuration adds clock disable option which can disable
      internal VCO clock. Before the system clock change, there is an restric-
      tion added to make sure clock disabled and not config any clock when no
      headset connected.
      
      In power management, we involve the solution about races and jack detec-
      tion in resume from Ben Zhang in the following patch and list his comment.
      [PATCH] ASoC: nau8825: Fix jack detection across suspend
      "Jack plug status is rechecked at resume to handle plug/unplug
      in S3 when the chip has no power."
      "Suspend/resume callbacks are moved from the i2c dev_pm_ops to
      snd_soc_codec_driver. soc_resume_deferred is a delayed work
      which may trigger nau8825_set_bias_level. The bias change races
      against dev_pm_ops, causing jack detection issues.
      soc_resume_deferred ensures bias change and snd_soc_codec_driver
      suspend/resume are sequenced correctly."
      
      Change SAR widget to supply type which can prevent the codec keeping at
      SND_SOC_BIAS_ON during suspend. The codec suspend function can just invoke
      normally.
      
      Before the system suspends, the driver turns off all interruptions. Keep
      the interruption quiet before resume setup completes. The ADC channel will
      be disabled which is needed for interruptions at audo mode.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      2ec30f60
    • J
      ASoC: nau8825: add programmable biquad filter control · 18d8306d
      John Hsu 提交于
      Add programmable biquad filter configuration control for user space.
      The filter is configurable for low pass filters, high pass filters,
      Notch filter, etc in the ADC and DAC path.
      Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      18d8306d
  19. 30 5月, 2016 6 次提交
  20. 28 3月, 2016 1 次提交
    • B
      ASoC: nau8825: Fix jack detection across suspend · e6cee900
      Ben Zhang 提交于
      Jack plug status is rechecked at resume to handle plug/unplug
      in S3 when the chip has no power.
      
      Suspend/resume callbacks are moved from the i2c dev_pm_ops to
      snd_soc_codec_driver. soc_resume_deferred is a delayed work
      which may trigger nau8825_set_bias_level. The bias change races
      against dev_pm_ops, causing jack detection issues.
      soc_resume_deferred ensures bias change and snd_soc_codec_driver
      suspend/resume are sequenced correctly.
      Signed-off-by: NBen Zhang <benzh@chromium.org>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      e6cee900
  21. 12 3月, 2016 1 次提交
  22. 17 11月, 2015 1 次提交
  23. 23 10月, 2015 2 次提交
  24. 08 10月, 2015 1 次提交
  25. 07 10月, 2015 2 次提交