- 12 11月, 2014 2 次提交
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由 Jean Delvare 提交于
The i2c-i801 driver can work without interrupts, so there is no reason to make a request_irq failure fatal. Instead we can simply fallback to polling. Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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由 Jean Delvare 提交于
Some systems have been reported to have trouble with interrupts. Use wait_event_timeout() instead of wait_event() so we don't get stuck in that case, and log the problem. Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 08 11月, 2014 1 次提交
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由 Wolfram Sang 提交于
We have a central copy of the GPL for that. Some addresses were already outdated. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
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- 16 10月, 2014 1 次提交
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This patch adds the I2C/SMBus Device IDs for the Intel Sunrise Point PCH. Signed-off-by: NJames Ralston <james.d.ralston@intel.com> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 19 8月, 2014 1 次提交
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由 Alan Cox 提交于
The SMBus host controller is the same as used in Baytrail so add the new PCI ID to the driver's list of supported IDs. Signed-off-by: NAlan Cox <alan@linux.intel.com> Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 18 7月, 2014 2 次提交
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由 Jean Delvare 提交于
Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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由 Jean Delvare 提交于
A long name broke the alignment, shift the columns a bit to fix it and make the table look nice again. While we're here, switch to the standard comment style to make checkpatch happy, and use tabs instead of spaces for column alignment. Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 13 3月, 2014 1 次提交
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由 Jingoo Han 提交于
Don't use DEFINE_PCI_DEVICE_TABLE macro, because this macro is not preferred. Signed-off-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 10 3月, 2014 1 次提交
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由 Chew, Kean ho 提交于
Add Device ID of Intel BayTrail SMBus Controller. Signed-off-by: NChew, Kean ho <kean.ho.chew@intel.com> Signed-off-by: NChew, Chiau Ee <chiau.ee.chew@intel.com> Reviewed-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 30 1月, 2014 1 次提交
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由 Jean Delvare 提交于
Signed-off-by: NJean Delvare <khali@linux-fr.org>
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- 15 11月, 2013 1 次提交
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由 James Ralston 提交于
This patch adds the SMBus Device IDs for the Intel Wildcat Point-LP PCH. Signed-off-by: NJames Ralston <james.d.ralston@intel.com> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 23 8月, 2013 1 次提交
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由 Wolfram Sang 提交于
I2C of helpers used to live in of_i2c.c but experience (from SPI) shows that it is much cleaner to have this in the core. This also removes a circular dependency between the helpers and the core, and so we can finally register child nodes in the core instead of doing this manually in each driver. So, fix the drivers and documentation, too. Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 21 6月, 2013 1 次提交
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由 Seth Heasley 提交于
This patch adds the i801 SMBus Controller DeviceIDs for the Intel Coleto Creek PCH. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 18 5月, 2013 1 次提交
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由 Jean Delvare 提交于
Duplicate the feature bits documentation in modinfo, as not every user will read the driver's source code or documentation file. Signed-off-by: NJean Delvare <khali@linux-fr.org> Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 22 2月, 2013 1 次提交
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由 Doug Anderson 提交于
There is simply no reason to be manually setting the private driver data to NULL in the remove/fail to probe cases. This is just extra cruft code that can be removed. A few notes: * Nothing relies on drvdata being set to NULL. * The __device_release_driver() function eventually calls dev_set_drvdata(dev, NULL) anyway, so there's no need to do it twice. * I verified that there were no cases where xxx_get_drvdata() was being called in these drivers and checking for / relying on the NULL return value. This could be cleaned up kernel-wide but for now just take the baby step and remove from the i2c subsystem. Reported-by: NWolfram Sang <wsa@the-dreams.de> Reported-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NDoug Anderson <dianders@chromium.org> Reviewed-by: NJean Delvare <khali@linux-fr.org> Acked-by: NPeter Korsgaard <jacmet@sunsite.dk> Reviewed-by: NMika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: NMarek Vasut <marex@denx.de> Signed-off-by: NWolfram Sang <wolfram@the-dreams.de>
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- 16 2月, 2013 1 次提交
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由 James Ralston 提交于
This patch adds the SMBus Device IDs for the Intel Wellsburg PCH Signed-off-by: NJames Ralston <james.d.ralston@intel.com> Reviewed-by: NJean Delvare <khali@linux-fr.org> Signed-off-by: NWolfram Sang <wolfram@the-dreams.de>
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- 09 2月, 2013 1 次提交
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由 Seth Heasley 提交于
This patch adds the PCU SMBus DeviceID for the Intel Avoton SOC. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Reviewed-by: NJean Delvare <khali@linux-fr.org> Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
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- 23 12月, 2012 1 次提交
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由 Bill Pemberton 提交于
CONFIG_HOTPLUG is going away as an option. As result the __dev* markings will be going away. Remove use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit. Signed-off-by: NBill Pemberton <wfp5p@virginia.edu> Acked-by: Peter Korsgaard <peter.korsgaard@barco.com> (for ocores and mux-gpio) Acked-by: Havard Skinnemoen <hskinnemoen@gmail.com> (for i2c-gpio) Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> (for puf3) Acked-by: Barry Song <baohua.song@csr.com> (for sirf) Reviewed-by: NJean Delvare <khali@linux-fr.org> [wsa: Fixed "foo* bar" flaws while we are here] Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
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- 17 12月, 2012 2 次提交
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由 Jean Delvare 提交于
I did not receive a single bug report after interrupt support was added for a limited number of chips. So I'd say the code is good and should be enabled for all supported chips, that is: ICH5 and later. Signed-off-by: NJean Delvare <khali@linux-fr.org> Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
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由 Thierry Reding 提交于
Add support for probing slave devices parsed from the device tree. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Acked-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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- 29 10月, 2012 2 次提交
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由 Jean Delvare 提交于
Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Jean Delvare 提交于
Arbitrarily selecting GPIOLIB causes trouble on some architectures, so don't do that. Instead, just make the optional multiplexing code depend on CONFIG_I2C_MUX_GPIO instead of CONFIG_I2C_MUX for now. We can revisit if the i2c-i801 driver ever supports other multiplexing flavors. Also make that optional code depend on DMI, as it won't do anything without that. Signed-off-by: NJean Delvare <khali@linux-fr.org> Cc: Fengguang Wu <fengguang.wu@intel.com>
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- 06 10月, 2012 2 次提交
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由 Jean Delvare 提交于
Now that i2c-mux-gpio is able to find the GPIO chip by itself, we can delegate this task. The great thing here is that i2c-mux-gpio can defer device probing until the gpio chip is available, so we no longer depend on the module loading order. Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Jean Delvare 提交于
Add support for SMBus multiplexing on Asus Z8 motherboard series. On these boards, the memory slots are behind a GPIO-controlled I2C multiplexer. Models with 6 or 12 memory slots have 2 segments behind the multiplexer, while models with 18 memory slots have 3 such segments. On these boards, only the memory slots are behind the multiplexer, so it is possible to keep the autodetection mechanism. The code is generic enough so it could work on other boards as long as the multiplexer is controlled by GPIO pins. For other forms of multiplexing (for example using an I2C device) additional code will be needed. Thanks to Asus for providing a board to develop and test this feature, as well as all the technical information required. At the moment, the GPIO driver must be loaded before the i2c-i801 driver, but I hope to solve this soon, using deferred probing on the i2c-mux-gpio side. Signed-off-by: NJean Delvare <khali@linux-fr.org>
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- 10 9月, 2012 1 次提交
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由 James Ralston 提交于
Add the SMBus Device IDs for the Intel Lynx Point-LP PCH. Signed-off-by: NJames Ralston <james.d.ralston@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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- 24 7月, 2012 9 次提交
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由 Daniel Kurtz 提交于
Byte-by-byte transactions are used primarily for accessing I2C devices with an SMBus controller. For these transactions, for each byte that is read or written, the SMBus controller generates a BYTE_DONE IRQ. The isr reads/writes the next byte, and clears the IRQ flag to start the next byte. On the penultimate IRQ, the isr also sets the LAST_BYTE flag. There is no locking around the cmd/len/count/data variables, since the I2C adapter lock ensures there is never multiple simultaneous transactions for the same device, and the driver thread never accesses these variables while interrupts might be occurring. The end result is faster I2C block read and write transactions. Note: This patch has only been tested and verified by doing I2C read and write block transfers on Cougar Point 6 Series PCH, as well as I2C read block transfers on ICH5. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Jean Delvare 提交于
Enable interrupts on more devices. ICH5, ICH7(-M) and ICH10 have been tested to work OK. ICH8 and ICH9 are expected to work just fine as they are very close to ICH7 and ICH10. Ultimately we want to enable this feature on at least every device since the ICH5, but for now we limit the exposure. We'll enable it for other devices if we don't get negative feedback. As a bonus, let the user know when interrupts are used. Signed-off-by: NJean Delvare <khali@linux-fr.org> Cc: Daniel Kurtz <djkurtz@chromium.org>
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由 Daniel Kurtz 提交于
Add a new 'feature' to i2c-i801 to enable using PCI interrupts. When the feature is enabled, then an isr is installed for the device's PCI IRQ. An I2C/SMBus transaction is always terminated by one of the following interrupt sources: FAILED, BUS_ERR, DEV_ERR, or on success: INTR. When the isr fires for one of these cases, it sets the ->status variable and wakes up the waitq. The waitq then saves off the status code, and clears ->status (in preparation for some future transaction). The SMBus controller generates an INTR irq at the end of each transaction where INTREN was set in the HST_CNT register. No locking is needed around accesses to priv->status since all writes to it are serialized: it is only ever set once in the isr at the end of a transaction, and cleared while no interrupts can occur. In addition, the I2C adapter lock guarantees that entire I2C transactions for a single adapter are always serialized. For this patch, the INTREN bit is set only for SMBus block, byte and word transactions, but not for I2C reads or writes. The use of the DS (BYTE_DONE) interrupt with byte-by-byte I2C transactions is implemented in a subsequent patch. The interrupt feature has only been enabled for COUGARPOINT hardware. In addition, it is disabled if SMBus is using the SMI# interrupt. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Jean Delvare 提交于
(Based on earlier work by Daniel Kurtz.) Come up with a consistent, driver-wide strategy for event polling. For intermediate steps of byte-by-byte block transactions, check for BYTE_DONE or any error flag being set. At the end of every transaction (regardless of PEC being used), check for both BUSY being cleared and INTR or any error flag being set. This ensures proper action for all transaction types. Signed-off-by: NJean Delvare <khali@linux-fr.org> Cc: Daniel Kurtz <djkurtz@chromium.org>
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由 Daniel Kurtz 提交于
Later patches enable interrupts. This preliminary patch removes the older unsupported ENABLE_INT9 flag. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Daniel Kurtz 提交于
Rename the SMBHSTCNT register bit access constants to match the style of other register bits. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Daniel Kurtz 提交于
If an error is detected in the polling loop, abort the transaction and return an error code. * DEV_ERR is set if the device does not respond with an acknowledge, and the SMBus controller times out (minimum 25ms). * BUS_ERR is set if a bus arbitration collision is detected. In other words, when the SMBus controller tries to generate a START condition, but detects that the SMBDATA is being held low, usually by another SMBus/I2C master. * FAILED is only set if a transaction is stopped by software (using the SMBHSTCNT KILL bit). Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Daniel Kurtz 提交于
Writing back the whole status register could clear unwanted bits. In particular, it could clear the "INUSE_STS" bit, which is a 'hardware semaphore', that might be useful to use some day. To prepare for this, let's ban writing back the whole status to register HST_STS, of which this is the only instance. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Daniel Kurtz 提交于
As a slight optimization, pull some logic out of the polling loop during byte-by-byte transactions by just setting the I801_LAST_BYTE bit, as defined in the i801 (PCH) datasheet, when reading the last byte of a byte-by-byte I2C_SMBUS_READ. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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- 27 3月, 2012 2 次提交
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由 Jean Delvare 提交于
Use usleep_range instead of msleep when waiting for command completion. Most SMBus commands complete in less than 2 jiffies so this brings a pleasant performance boost. Strongly inspired from a similar change by Olivier Sobrie to the i2c-isch driver. Signed-off-by: NJean Delvare <khali@linux-fr.org> Cc: Olivier Sobrie <olivier@sobrie.be>
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由 Seth Heasley 提交于
Add the SMBus controller device IDs for the Intel Lynx Point PCH. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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- 13 1月, 2012 1 次提交
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由 Axel Lin 提交于
Convert static struct pci_device_id *[] to static DEFINE_PCI_DEVICE_TABLE tables. Use DEFINE_PCI_DEVICE_TABLE ensures we make the pci_device_id table const and marked as __devinitconst. This also fixes some warnings from checkpatch: e.g. WARNING: Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id #1096: FILE: i2c/busses/i2c-intel-mid.c:1096: +static struct pci_device_id intel_mid_i2c_ids[] = { Signed-off-by: NAxel Lin <axel.lin@gmail.com> Cc: Rudolf Marek <r.marek@assembler.cz> Cc: Ben Dooks <ben-linux@fluff.org> Acked-by: NOlof Johansson <olof@lixom.net> Cc: "Mark M. Hoffman" <mhoffman@lightlink.com> Acked-by: NDirk Brandewie <dirk.brandewie@gmail.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Acked-by: NWolfram Sang <w.sang@pengutronix.de> Cc: Feng Tang <feng.tang@intel.com> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NJean Delvare <khali@linux-fr.org>
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- 25 5月, 2011 3 次提交
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由 Jean Delvare 提交于
Don't let other driver config options influence us, as it makes the code more complex and fragile for a small benefit. There's nothing wrong with instantiating I2C devices even if they don't have a driver. And we're talking about 835 extra bytes in the binary on x86-64, that's hardly worth arguing about. Signed-off-by: NJean Delvare <khali@linux-fr.org> Cc: David Woodhouse <david.woodhouse@intel.com> Cc: Hans de Goede <hdegoede@redhat.com>
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由 Jean Delvare 提交于
Scanning the BIOS memory for the apanel information is costly, so avoid doing it on non-Fujitsu machines. Signed-off-by: NJean Delvare <khali@linux-fr.org>
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由 Jean Delvare 提交于
I don't know if Fujitsu is ever going to produce Patsburg-based machines, but if they do, I'd rather not probe the secondary (IDF) SMBus channels. At least not until we have a good reason for doing so. On a side note, I'm not even sure if it is right to enable detection of HWMON and DDC devices on the IDF channels. Time will tell... Signed-off-by: NJean Delvare <khali@linux-fr.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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