Add the Video Processing Unit node for RK3288 SoC.

Fix the VPU IOMMU node, which was disabled and lacking
its power domain property.
Reviewed-by: NTomasz Figa <tfiga@chromium.org>
Signed-off-by: NEzequiel Garcia <ezequiel@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.

Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Fix other missing properties (clocks, OPP, clock latency) as well to
make it all work.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
[follow conversion to operating-points-v2]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Operating points need to be present in each cpu core using it, not only
the first one. With operating-points-v1 this would require duplicating
this table into each cpu node.

With opp-v2 we can share the same table on all nodes.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

Update all 32bit rockchip devicetree files to use SPDX-License-Identifiers.

All files except rk3288-veyron-analog-audio.dtsi (which is GPL 2.0 only)
claim to be GPL and X11 while the actual license text is MIT. Use the
MIT SPDX tag for them.
Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: NBrian Norris <briannorris@chromium.org>
Acked-by: NMatthias Brugger <mbrugger@suse.com>
Acked-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add clocks in iommu nodes, since we are going to control clocks in
rockchip iommu driver.
Signed-off-by: NJeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

According to TRM, uart4 tx/rx should be 14/15
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

dtc now gives the following warning:

arch/arm/boot/dts/rk3288-tinker.dtb: Warning (sound_dai_property): /sound/simple-audio-card,codec: Missing property '#sound-dai-cells' in node /hdmi@ff980000 or bad phandle (referred from sound-dai[0])

Add the missing #sound-dai-cells property.

Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The interrupts property in the iep-IOMMU node for the rk3288 dts file has a
spurious extra cell causing a dtc warning:

Warning (interrupts_property): interrupts size is (16), expected multiple of 12 in /iommu@ff900800

Remove the extra cell.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The CEC line can be routed to two possible pins. Define those pins.
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The dw-hdmi block needs the cec clk for the rk3288. Add it.
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add the RGA dt config of rk3288 SoC.
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add LVDS info in rk3288.dtsi for LVDS driver
Signed-off-by: NSandy Huang <hjc@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add IEP/ISP/VPU/HEVC iommu nodes
Signed-off-by: NSimon Xue <xxm@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Signed-off-by: NTao Huang <huangtao@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The binding specifies the actual implementations only (mali-t760
for example) but not the arm,mali-midgard used in some vendor kernels.
So drop that compatible property from the rk3288 where it had slipped in.

Also fix the node name which should be a generic gpu@...
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add Mali GPU device tree node for the rk3288 SoC, with devfreq
opp table.
Signed-off-by: NGuillaume Tucker <guillaume.tucker@collabora.com>
Tested-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

dw-mmc got its reset-properties specified, so add the softresets
for it in rk3288.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviwed-by: NShawn Lin <shawn.lin@rock-chips.com>

Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.
Acked-by: NShawn Guo <shawnguo@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

when pd power on/off, the qos regs need to save and restore.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This is not needed as the gadget now fully supports DMA and it can
autodetect it. This was initially added because gadget DMA mode was only
partially implemented so could not be automatically enabled.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

In drivers/mmc/core/host.c, there is "max-frequency" property.
It should be same behavior. So use the "max-frequency" instead of
"clock-freq-min-max".
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Signed-off-by: NFinley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

The disassembled DTB are almost the same, besides empty chosen nodes
being removed. So the change should not have a functional impact.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>

Rockchip platform use a SYSCON mapped register store
the reboot mode magic value for bootloader to use when
system reboot. So add syscon-reboot-mode driver DT node
for rk3xxx/rk3036/rk3288 based platform
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The rk3288 usbphy is completely enclosed in the general register files
and the updated binding allows it to be a subnode of the GRF now.
So move the node appropriately.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

In order to use Wake-on-Lan on RK3288 integrated MAC, we need to wake-up
the CPU on the PMT interrupt when the MAC and the PHY are in low power mode.
Adding the interrupt declaration.
Signed-off-by: NVincent Palatin <vpalatin@chromium.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

io-voltage control is actually part of the grf, so move the node under the
newly available grf simple-mfd.

To minimize duplicate code, the core node and compatible property
gets placed in the core rk3288.dtsi while the individual boards
now only need to enable it and add the necessary supply properties.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

In order to be standard to manage for rockchip SoCs,  move the thermal
data into rk3288 dtsi, we needn't to add a new file for thermal.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The edp-phy control is a part of the General Register Files and
with a recent patch in 4.6 the phy driver can now also handle this
correctly, so move the dts node under the GRF as well.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Similar to the pmu, the general register files contain a lot of different
setting bits grouped into general registers, but also some somewhat special
entities like the controls for some phy-blocks or the io-voltage control.
To be able to move these blocks under the grf node where they actually
belong, make it a simple-mfd.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The edp hotplug pin is fixed on the soc side, anybody wanting to use it
will need the same definition anyway, so move it to a common location.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDouglas Anderson <dianders@chromium.org>

Add the rk3288 edp node and its hooks into the display-subsystem.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDouglas Anderson <dianders@chromium.org>

Add the core device node of the edp-phy on rk3288 socs.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDouglas Anderson <dianders@chromium.org>

The mipi controller node does contain an unused reg property as well as
unnecessary #address-cells and #size-cells properties for subnodes
not using addresses, so remove those to also make dtc happy.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NRob Herring <robh@kernel.org>

The usbphy subnodes do have a reg property but no unitname, add them.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NRob Herring <robh@kernel.org>

The power-domain sub-nodes do have reg properties, but so far are
missing the expected unit names. So add the missing ones.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NRob Herring <robh@kernel.org>

The MIPI controllers are part of the VIO power domain so add the
necessary property to indicate this for the controller we support.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

These must be translated from the values in the TRM by subtracting 32,
which has not been done.  The SPDIF interrupt is also off-by-one.
Signed-off-by: NJohn Keeping <john@metanate.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>