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  1. 18 12月, 2015 2 次提交
    • K
      Input: goodix - add axis swapping and axis inversion support · ad48cf5e
      由 Karsten Merker 提交于 
      Implement support for the following device-tree and ACPI 5.1 DSD
properties in the goodix touchscreen driver:

 - touchscreen-inverted-x:  X axis is inverted (boolean)
 - touchscreen-inverted-y:  Y axis is inverted (boolean)
 - touchscreen-swapped-x-y: X and Y axis are swapped (boolean)

These are necessary on tablets which have a display in portrait
format while the touchscreen is in landscape format, such as e.g.
the MSI Primo 81.
Signed-off-by: NKarsten Merker <merker@debian.org>
Tested-by: NBastien Nocera <hadess@hadess.net>
Tested-by: Irina Tirdea <irina.tirdea@intel.com> (with ACPI DSD properties)
Tested-by: Aleksei Mamlin <mamlinav@gmail.com> (with device-tree properties)
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
      ad48cf5e
    • I
      Input: goodix - reset device at init · ec6e1b40
      由 Irina Tirdea 提交于 
      After power on, it is recommended that the driver resets the device.
The reset procedure timing is described in the datasheet and is used
at device init (before writing device configuration) and
for power management. It is a sequence of setting the interrupt
and reset pins high/low at specific timing intervals. This procedure
also includes setting the slave address to the one specified in the
ACPI/device tree.

This is based on Goodix datasheets for GT911 and GT9271 and on Goodix
driver gt9xx.c for Android (publicly available in Android kernel
trees for various devices).

For reset the driver needs to control the interrupt and
reset gpio pins (configured through ACPI/device tree). For devices
that do not have the gpio pins properly declared, the functionality
depending on these pins will not be available, but the device can still
be used with basic functionality.

For both device tree and ACPI, the interrupt gpio pin configuration is
read from the "irq-gpios" property and the reset pin configuration is
read from the "reset-gpios" property. For ACPI 5.1, named properties
can be specified using the _DSD section. This functionality will not be
available for devices that use indexed gpio pins declared in the _CRS
section (we need to provide backward compatibility with devices
that do not support using the interrupt gpio pin as output).

For ACPI, the pins can be specified using ACPI 5.1:
Device (STAC)
{
    Name (_HID, "GDIX1001")
    ...

    Method (_CRS, 0, Serialized)
    {
        Name (RBUF, ResourceTemplate ()
        {
            I2cSerialBus (0x0014, ControllerInitiated, 0x00061A80,
                AddressingMode7Bit, "\\I2C0",
                0x00, ResourceConsumer, ,
                )

            GpioInt (Edge, ActiveHigh, Exclusive, PullNone, 0x0000,
                "\\I2C0", 0x00, ResourceConsumer, ,
                 )
                 {   // Pin list
                     0
                 }

            GpioIo (Exclusive, PullDown, 0x0000, 0x0000,
                IoRestrictionOutputOnly, "\\I2C0", 0x00,
                ResourceConsumer, ,
                )
                {
                     1
                }
        })
        Return (RBUF)
    }

    Name (_DSD,  Package ()
    {
        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
        Package ()
        {
            Package (2) {"irq-gpios", Package() {^STAC, 0, 0, 0 }},
            Package (2) {"reset-gpios", Package() {^STAC, 1, 0, 0 }},
            ...
        }
    }
Signed-off-by: NOctavian Purdila <octavian.purdila@intel.com>
Signed-off-by: NIrina Tirdea <irina.tirdea@intel.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NBastien Nocera <hadess@hadess.net>
Tested-by: NBastien Nocera <hadess@hadess.net>
Tested-by: NAleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
      ec6e1b40
  3. 12 12月, 2015 1 次提交
  5. 03 12月, 2015 1 次提交
    • M
      net: mvneta: enable setting custom TX IP checksum limit · 9110ee07
      由 Marcin Wojtas 提交于 
      Since Armada 38x SoC can support IP checksum for jumbo frames only on
a single port, it means that this feature should be enabled per-port,
rather than for the whole SoC.

This patch enables setting custom TX IP checksum limit by adding new
optional property to the mvneta device tree node. If not used, by
default 1600B is set for "marvell,armada-370-neta" and 9800B for other
strings, which ensures backward compatibility. Binding documentation
is updated accordingly.
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9110ee07
  7. 13 11月, 2015 1 次提交
  9. 11 11月, 2015 2 次提交
  11. 10 11月, 2015 3 次提交
  13. 08 11月, 2015 2 次提交
  15. 05 11月, 2015 1 次提交
  17. 04 11月, 2015 2 次提交
  19. 03 11月, 2015 9 次提交
  21. 01 11月, 2015 1 次提交
  23. 31 10月, 2015 13 次提交
  25. 30 10月, 2015 1 次提交
  27. 28 10月, 2015 1 次提交