- 20 4月, 2010 1 次提交
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由 Daniel Vetter 提交于
Just preparation, no functional change. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Acked-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 19 4月, 2010 1 次提交
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由 Adam Jackson 提交于
This should be a small power savings. Tested on Lenovo T410 (Ironlake), LVDS VGA and DisplayPort, up to 1920x1200R. v2: Add Sandybridge support, fix obvious math error. Acked-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 13 4月, 2010 12 次提交
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由 Zhenyu Wang 提交于
Update the self-refresh watermark for display plane/cursor and enable the memory self-refresh on Ironlake. The watermark is also updated for the active display plane. More than 1W idle power is saved on one Ironlake laptop after enabling memory self-refresh. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
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由 Zhao Yakui 提交于
Previously, after setting up the Pineview CxSR state, i9xx_update_wm would get called and overwrite our state. BTW: We will disable the self-refresh and never enable it any more if we can't find the appropriate the latency on pineview plaftorm. In such case the update_wm callback will be NULL. The bitmask macro is also defined to access the corresponding fifo watermark register. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
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由 Zhao Yakui 提交于
SDVO on Ibexpeak PCH with Ironlake is multiplexed with HDMIB port, and only has SDVOB port. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
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由 Carl Worth 提交于
The existing code handling the DPMS ON event is much more careful to ensure that these registers are enabled according to strict sequencing requirements. Enabling these early in mode_set simply defeats that. Signed-off-by: NCarl Worth <cworth@cworth.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
Added by original eDP support patch, not used any more. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
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由 Zhenyu Wang 提交于
As all display drivers have been converted, remove the left reference for connector object in old structure. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
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由 Zhenyu Wang 提交于
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
DP on Cougarpoint has new training pattern definitions, and new transcoder DP control register is used to determine the mapping for transcoder and DP digital output. And eDP for Sandybridge has new voltage and pre-emphasis level definitions. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
Fix the transcoder select bit for LVDS on CPT. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
Cougarpoint is the new PCH for Sandybridge CPU. This one resolves the chipset change for display pipeline compared to previous Ibexpeak PCH. Sandybridge/Cougarpoint has different FDI training parameters, so this also makes seperate FDI training functions for IBX and CPT. Other change includes new transcoder DPLL select function to set which DPLL for transcoder to pick up. And with another new transcoder C introduced in Cougarpoint, each connector has new transcoder select bits. This one adds that change to light up VGA. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Eric Anholt 提交于
Based on a patch by Zhao Yakui. Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Adam Jackson 提交于
The gen4 docs say it works, so why not. Tested on Ironlake. Signed-off-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 10 4月, 2010 3 次提交
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由 Zhenyu Wang 提交于
In load detection, connector's encoder assignment must be kept consistent for proper mode setting, and this makes connector as explicit parameter for load detect function to not require single data structure to hold both encoder and connector reference, ease the transition for splitted encoder/connector model. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
For introducing splitted encoder/connector structure, this helper will return connector's attached encoder when needed. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
What we really want is encoder info instead of connector, so change some more list walk in pipeline setup functions from connector_list to encoder_list. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 07 4月, 2010 1 次提交
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由 Dave Airlie 提交于
The fbdev layer in the kms code should act like a consumer of the kms services and avoid having relying on information being store in the kms core structures in order for it to work. This patch a) removes the info pointer/psuedo palette from the core drm_framebuffer structure and moves it to the fbdev helper layer, it also removes the core drm keeping a list of kernel kms fbdevs. b) migrated all the fb helper functions out of the crtc helper file into the fb helper file. c) pushed the fb probing/hotplug control into the driver d) makes the surface sizes into a structure for ease of passing This changes the intel/radeon/nouveau drivers to use the new helper. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 30 3月, 2010 1 次提交
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由 Tejun Heo 提交于
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: NTejun Heo <tj@kernel.org> Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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- 26 3月, 2010 4 次提交
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由 Eric Anholt 提交于
Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Eric Anholt 提交于
The intel_output naming is inherited from the UMS code, which had a structure of screen -> CRTC -> output. The DRM code has an additional notion of encoder/connector, so the structure is screen -> CRTC -> encoder -> connector. This is a useful structure for SDVO encoders which can support multiple connectors (each of which requires different programming in the one encoder and could be connected to different CRTCs), or for DVI-I, where multiple encoders feed into the connector for whether it's used for digital or analog. Most of our code is encoder-related, so transition it to talking about encoders before we start trying to distinguish connectors. This patch is produced by sed s/intel_output/intel_encoder/ over the driver. Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Daniel Vetter 提交于
This is a purely cosmetic change to make changes in this area easier. And hey, it's not only clearer and typechecked, but actually shorter, too! [anholt: To clarify, this is a change to let us later make drm_i915_gem_object subclass drm_gem_object, instead of having drm_gem_object have a pointer to i915's private data] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Acked-by: NDave Airlie <airlied@gmail.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Robert Hooker 提交于
It is causing hangs after a suspend/resume cycle with the default powersave=1 module option on these chipsets since 2.6.32-rc. BugLink: http://bugs.launchpad.net/bugs/492392Signed-off-by: NRobert Hooker <sarvatt@ubuntu.com> Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 19 3月, 2010 1 次提交
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由 Eric Anholt 提交于
Signed-off-by: NEric Anholt <eric@anholt.net>
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- 18 3月, 2010 1 次提交
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由 Priit Laes 提交于
Signed-off-by: NPriit Laes <plaes@plaes.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 27 2月, 2010 3 次提交
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由 Eric Anholt 提交于
I think this is pretty much correct. Not really tested. Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Eric Anholt 提交于
I can't explain this, except that it makes my display correct. Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Eric Anholt 提交于
Signed-off-by: NEric Anholt <eric@anholt.net>
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- 23 2月, 2010 6 次提交
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由 Jesse Barnes 提交于
Tools like powertop want to check the current FBC status and report it to the user. So add a debugfs file indicating whether FBC is enabled, and if not, why. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Jesse Barnes 提交于
At unload time, we need to disable DRPS, but we need to do it correctly or the GPU will hang and we won't be able to load the module again. So set the SFCAVM bit so we can properly restore the DRPS config at unload. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Li Peng 提交于
He Shuang reported an OGLC performance regression introduced in the patch "enable memory self refresh on 9xx", In that patch, SR on 945 is disabled everytime when calling intel_mark_busy(), while too much of such operation will impact performance. Actually disable SR is necessary only when GPU and Crtc changing from idle to busy. This patch make such optimization. It fixes upstream bug http://bugs.freedesktop.org/show_bug.cgi?id=26422Signed-off-by: NLi Peng <peng.li@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Matthew Garrett 提交于
The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: NMatthew Garrett <mjg@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Jesse Barnes 提交于
Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: Nykzhao <yakui.zhao@intel.com> [anholt: Resolved against the irq handler loop removal] Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Li Peng 提交于
Enabling memory self refresh (SR) on 9xx needs to set additional register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the write to self refresh bit and bit 16 to enable the write of self refresh watermark. On 915, bit 12 of INSTPM is used to enable SR. SR will take effect when CPU enters C3+ state and its entry/exit should be automatically controlled by H/W, driver only needs to set SR enable bits in wm update. But this isn't safe in my test on 945 because GPU is hung. So this patch explicitly enables SR when GPU is idle, and disables SR when it is busy. In my test on a netbook of 945GSE chipset, it saves about 0.8W idle power. Signed-off-by: NLi Peng <peng.li@intel.com> [anholt: rebased against 33c5fd12 by adding disable of INSTPM SR bit on 915GM for two pipe setup] Signed-off-by: NEric Anholt <eric@anholt.net>
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- 11 2月, 2010 6 次提交
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由 Luca Barbieri 提交于
Mostly obvious simplifications. The i915 pread/pwrite ioctls, intel_overlay_put_image and nouveau_gem_new were incorrectly using the locked versions without locking: this is also fixed in this patch. Signed-off-by: NLuca Barbieri <luca@luca-barbieri.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Jesse Barnes 提交于
This will prevent things from falling over if the user frees the flip buffer before we complete the flip, since we'll hold an internal reference. Reported-by: NKristian Høgsberg <krh@bitplanet.net> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
The MI_DISPLAY_FLIP command needs to be set the same pipe source image like in pipe source register, e.g source image size minus one. This fixes screen corrupt issue on Ironlake. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Jesse Barnes 提交于
When a new page flip is requested, we need to both queue an unpin for the current framebuffer, and also increment the flip pending count on the newly submitted buffer. At flip finish time, we need to unpin the old fb and decrement the flip pending count on the new buffer. The old code was conflating the two, and led to hangs when new direct rendered apps were started, replacing the existing frame buffer. This patch splits out the buffers and prevents the hangs. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NKristian Høgsberg <krh@bitplanet.net> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Jesse Barnes 提交于
On 945, we need to avoid entering self-refresh if the compressor is busy, or we may cause display FIFO underruns leading to ugly flicker. Fixes fdo bug #24314, kernel bug #15043. Tested-by: NAlexander Lam <lambchop468@gmail.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Julien Cristau <jcristau@debian.org> (fd.o #25371) Cc: stable@kernel.org Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
Got Ironlake DPLL parameter table, which reflects the hardware optimized values. So this one trys to list DPLL parameters for different output types, should potential fix clock issue seen on new Arrandale CPUs. This fixes DPLL setting failure on one 1920x1080 dual channel LVDS for Ironlake. Test has also been made on LVDS panels with smaller size and CRT/HDMI/DP ports for different monitors on their all supported modes. Update: - Change name of double LVDS to dual LVDS. - Fix SSC 120M reference clock to use the right range. Cc: CSJ <changsijay@gmail.com> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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