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  1. 16 2月, 2010 1 次提交
  3. 25 11月, 2009 1 次提交
  5. 29 5月, 2009 2 次提交
    • M
      [ARM] Add cmpxchg support for ARMv6+ systems (v5) · ecd322c9
      由 Mathieu Desnoyers 提交于 
      Add cmpxchg/cmpxchg64 support for ARMv6K and ARMv7 systems
(original patch from Catalin Marinas <catalin.marinas@arm.com>)

The cmpxchg and cmpxchg64 functions can be implemented using the
LDREX*/STREX* instructions. Since operand lengths other than 32bit are
required, the full implementations are only available if the ARMv6K
extensions are present (for the LDREXB, LDREXH and LDREXD instructions).

For ARMv6, only 32-bits cmpxchg is available.

Mathieu :

Make cmpxchg_local always available with best implementation for all type sizes (1, 2, 4 bytes).
Make cmpxchg64_local always available.

Use "Ir" constraint for "old" operand, like atomic.h atomic_cmpxchg does.

Change since v3 :
- Add "memory" clobbers (thanks to Nicolas Pitre)
- removed __asmeq(), only needed for old compilers, very unlikely on ARMv6+.

Note : ARMv7-M should eventually be ifdefed-out of cmpxchg64. But it's not
supported by the Linux kernel currently.

Put back arm < v6 cmpxchg support.
Signed-off-by: NMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Nicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ecd322c9
    • R
      [ARM] barriers: improve xchg, bitops and atomic SMP barriers · bac4e960
      由 Russell King 提交于 
      Mathieu Desnoyers pointed out that the ARM barriers were lacking:

- cmpxchg, xchg and atomic add return need memory barriers on
  architectures which can reorder the relative order in which memory
  read/writes can be seen between CPUs, which seems to include recent
  ARM architectures. Those barriers are currently missing on ARM.

- test_and_xxx_bit were missing SMP barriers.

So put these barriers in.  Provide separate atomic_add/atomic_sub
operations which do not require barriers.
Reported-Reviewed-and-Acked-by: NMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      bac4e960
  7. 25 3月, 2009 1 次提交
  9. 20 3月, 2009 1 次提交
    • R
      [ARM] pass reboot command line to arch_reset() · be093beb
      由 Russell King 提交于 
      OMAP wishes to pass state to the boot loader upon reboot in order to
instruct it whether to wait for USB-based reflashing or not.  There is
already a facility to do this via the reboot() syscall, except we ignore
the string passed to machine_restart().

This patch fixes things to pass this string to arch_reset().  This means
that we keep the reboot mode limited to telling the kernel _how_ to
perform the reboot which should be independent of what we request the
boot loader to do.
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      be093beb
  11. 29 11月, 2008 1 次提交
  13. 07 11月, 2008 1 次提交
  15. 01 9月, 2008 1 次提交
  17. 03 8月, 2008 1 次提交
  19. 23 5月, 2008 1 次提交
  21. 08 2月, 2008 1 次提交
  23. 10 1月, 2008 1 次提交
  25. 20 7月, 2007 1 次提交
  27. 09 5月, 2007 4 次提交
  29. 22 4月, 2007 1 次提交
  31. 02 4月, 2007 1 次提交
  33. 02 3月, 2007 1 次提交
  35. 08 2月, 2007 2 次提交
  37. 18 12月, 2006 1 次提交
  39. 14 12月, 2006 1 次提交
  41. 09 12月, 2006 1 次提交
    • R
      [ARM] Handle HWCAP_VFP in VFP support code · efe90d27
      由 Russell King 提交于 
      Don't set HWCAP_VFP in the processor support file; not only does it
depend on the processor features, but it also depends on the support
code being present.  Therefore, only set it if the support code
detects that we have a VFP coprocessor attached.

Also, move the VFP handling of the coprocessor access register into
the VFP support code.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      efe90d27
  43. 28 9月, 2006 1 次提交
    • H
      [ARM] nommu: manage the CP15 things · f12d0d7c
      由 Hyok S. Choi 提交于 
      All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.
Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      f12d0d7c
  45. 25 9月, 2006 1 次提交
  47. 20 9月, 2006 1 次提交
  49. 15 7月, 2006 1 次提交
    • S
      [PATCH] remove set_wmb - arch removal · 52393ccc
      由 Steven Rostedt 提交于 
      set_wmb should not be used in the kernel because it just confuses the
code more and has no benefit.  Since it is not currently used in the
kernel this patch removes it so that new code does not include it.

All archs define set_wmb(var, value) to do { var = value; wmb(); }
while(0) except ia64 and sparc which use a mb() instead.  But this is
still moot since it is not used anyway.

Hasn't been tested on any archs but x86 and x86_64 (and only compiled
tested)
Signed-off-by: NSteven Rostedt <rostedt@goodmis.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      52393ccc
  51. 20 6月, 2006 1 次提交
  53. 01 6月, 2006 1 次提交
  55. 26 4月, 2006 1 次提交
  57. 29 3月, 2006 1 次提交
    • L
      [ARM] 3377/2: add support for intel xsc3 core · 23bdf86a
      由 Lennert Buytenhek 提交于 
      Patch from Lennert Buytenhek

This patch adds support for the new XScale v3 core.  This is an
ARMv5 ISA core with the following additions:

- L2 cache
- I/O coherency support (on select chipsets)
- Low-Locality Reference cache attributes (replaces mini-cache)
- Supersections (v6 compatible)
- 36-bit addressing (v6 compatible)
- Single instruction cache line clean/invalidate
- LRU cache replacement (vs round-robin)

I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
cores have separate errata and have to handle things like L2, so it
is simpler to keep it separate.

L2 cache support is currently a build option because the L2 enable
bit must be set before we enable the MMU and there is no easy way to
capture command line parameters at this point.

There are still optimizations that can be done such as using LLR for
copypage (in theory using the exisiting mini-cache code) but those
can be addressed down the road.
Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      23bdf86a
  59. 16 3月, 2006 1 次提交
  61. 13 1月, 2006 2 次提交
  63. 17 11月, 2005 1 次提交
  65. 27 7月, 2005 2 次提交