This patch allows to create separate irq_set_wake and irq_set_type
implementations for different Tegra designs PMC that has different
wake models which require difference wake registers and different
programming sequence.

AOWAKE model support is available for Tegra186 and Tegra194 only
and it resides within PMC and supports tiered wake architecture.

Tegra210 and prior Tegra designs uses PMC directly to receive wake
events and coordinate the wake sequence.
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Interrupts that don't have an associated wake event or GPIO wake events
end up with an associate IRQ chip that is NULL and which causes IRQ code
to crash. This is because we don't implicitly set the parent IRQ chip by
allocating the interrupt at the parent. However, there really isn't a
corresponding interrupt at the parent, so we need to work around this by
setting the special no_irq_chip as the IRQ chip for these interrupts.

Fixes: 19906e6b ("soc/tegra: pmc: Add wake event support")
Signed-off-by: NThierry Reding <treding@nvidia.com>

tegra_powergate_sequence_power_up() powers up partition and also enables
clock & reset. However, if a controller like PCIe have multiple clocks
& resets and they need to be enabled in a sequence, driver must use
standalone function tegra_powergate_power_on() to power up partition.

Export tegra_powergate_power_on() to allow Tegra controller drivers to
unpower gate partition independent to clock & reset.
Signed-off-by: NManikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NThierry Reding <treding@nvidia.com>

Based on 1 normalized pattern(s):

  this software is licensed under the terms of the gnu general public
  license version 2 as published by the free software foundation and
  may be copied distributed and modified under those terms this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 285 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NAlexios Zavras <alexios.zavras@intel.com>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add some comments to clarify the purpose of the wake event support
implemented in the PMC driver.
Reviewed-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

For interrupts that are not wakeup sources but that may end up getting
mapped through the PMC as interrupt parent (this can happen for GPIOs),
return early in order to avoid a subsequent crash from an out-of-bounds
access to the register region.
Reported-by: NBitan Biswas <bbiswas@nvidia.com>
Reviewed-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The code currently doesn't support allocating more than one wake IRQ at
a time. Detect this situation and error out. Also make sure to output a
warning when that happens to help track down callers.
Reviewed-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 8df12745 ("soc/tegra: pmc: Enable XUSB partitions on boot")
was added as a workaround to ensure that the XUSB powergates or domains
were turned on early during boot because as this time the Tegra XHCI
driver did not handle the power domains at all. Now that the Tegra XHCI
driver has been updated to properly managed the power domains, the
workaround to enable the XUSB power domain early has been removed. This
also means that we can now move the initialisation of the powergates
into the PMC driver probe. Therefore, move the powergate initialisation
into the PMC driver probe and return any errors detected. To handle any
errors, functions to cleanup and remove any power-domains registered
with the generic power-domain framework have been added.

Finally the initialisation of the 'powergates_available' bitmask is kept
in the PMC early init function to allow the legacy PMC powergate APIs to
be called during early boot for enabling secondary CPUs on 32-bit Tegra
devices.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 5f84bb1a ("soc/tegra: pmc: Add sysfs entries for reset info")
added sysfs entries for Tegra reset source and level. However, these
sysfs are not removed on error and so if the registering of PMC device
is probe deferred, then the next time we attempt to probe the PMC device
warnings such as the following will be displayed on boot ...

  sysfs: cannot create duplicate filename '/devices/platform/7000e400.pmc/reset_reason'

Fix this by calling device_remove_file() for each sysfs entry added on
failure. Note that we call device_remove_file() unconditionally without
checking if the sysfs entry was created in the first place, but this
should be OK because kernfs_remove_by_name_ns() will fail silently.

Fixes: 5f84bb1a ("soc/tegra: pmc: Add sysfs entries for reset info")
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 5f84bb1a ("soc/tegra: pmc: Add sysfs entries for reset info")
added support for reading the Tegra reset source and level from sysfs.
However, there are a few issues with this commit which are ...
1. The number of reset sources for Tegra210 is defined as 5 but it
   should be 6.
2. The number of reset sources for Tegra186 is defined as 13 but it
   should be 15.
3. The SoC data variables num_reset_sources and num_reset_levels are
   defined but never used.

Fix the above by ...

1. Removing the reset source 'AOTAG' from the tegra30_reset_sources
   because this is only applicable for Tegra210.
2. Adding a new tegra210_reset_sources structure for Tegra210 reset
   sources.
3. Correct the number of reset sources for Tegra210 and Tegra186 by
   using the ARRAY_SIZE macro.
4. Updating the functions reset_reason_show() and reset_level_show()
   to check whether the value read is valid. While we are at it
   clean-up these functions to remove an unnecessary u32 variable.

Fixes: 5f84bb1a ("soc/tegra: pmc: Add sysfs entries for reset info")
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

By implementing the acquire/release protocol, the resets can be shared
with other drivers that also adhere to this protocol. This will be used
for example by the SOR driver to put hardware into a known good state,
irrespective of whether or not the power domain can be reset.
Signed-off-by: NThierry Reding <treding@nvidia.com>

On Tegra210 systems with new enough boot software, direct register
accesses to PMC register space from the non-secure world are not
allowed. Instead a monitor call may be used to read and write PMC
registers.

Add code to detect such a system by attempting to write a scratch
register and detecting if the write happened or not. If not, we switch
to doing all register accesses through the monitor call.
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>

It's not strictly necessary to initialize the fields in struct
tegra_pmc_soc if they are 0/false. However, we already initialize them
explicitly even if unnecessary, so keep doing that for consistency.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>

Some recently added code used weird alignment and indentation. Fix these
occurrences to make them consistent with the rest of the code.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>

Instead of using the global pmc variable, pass around a pointer where
possible. Also, replace most occurrences of pr_*() functions by their
equivalent dev_*() functions, reusing the pmc->dev pointer.

It's not possible to get completely rid of the global variable because
some of the public API that this driver exposes still relies on it.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>

Now there are no more external users of tegra_powergate_is_powered(),
make this a local function.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Some of the fields in struct tegra_pmc had not been documented when they
were added. Add the missing kerneldoc.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>

This will make it easier to insert new includes in the right place in
subsequent patches.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>

The new prefix allows the GPIOs to be uniquely identified on a per-chip
basis, which makes it easier to distinguish Tegra186 specific GPIOs from
those of later chips such as Tegra194 which supports a very different
set of GPIOs.
Signed-off-by: NThierry Reding <treding@nvidia.com>

When CONFIG_SMP is disabled, the tegra clk driver now fails to build:

drivers/clk/tegra/clk-tegra30.c: In function ‘tegra30_cpu_rail_off_ready’:
drivers/clk/tegra/clk-tegra30.c:1151:2: error: implicit declaration of function ‘tegra_pmc_cpu_is_powered’ [-Werror=implicit-function-declaration]
  cpu_pwr_status = tegra_pmc_cpu_is_powered(1) ||
    ^
Fix the above error by removing the CONFIG_SMP ifdef around the
declaration around the PMC CPU APIs because although these are not
needed for non-SMP configurations, there is no harm in including these
for non-SMP builds either.

Fixes: 61866523ed6e ("clk: tegra30: Use Tegra CPU powergate helper function")
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Tegra194 supports 96 wake events in total. Many of them are never used,
so only the most common ones (RTC alarm and power key) are currently
defined.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra186 support 96 wake events in total. Many of them are never used,
so only the most common ones (RTC alarm and power key) are currently
defined.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The power management controller has top-level controls that allow
certain interrupts (such as from the RTC or a subset of GPIOs) to
wake the system from sleep. Implement infrastructure to support
these wake events.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The PMC controller on Tegra194 has a couple of new I/O pads and drops
others compared to Tegra186.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
Signed-off-by: NYangtao Li <tiny.windzz@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This fixes splats like the one below if CONFIG_DEBUG_ATOMIC_SLEEP=y
and machine (Tegra30) booted with SMP=n or all secondary CPU's are put
offline. Locking isn't needed because it protects atomic operation.

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:254
in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/0
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G         C        4.18.0-next-20180821-00180-gc3ebb6544e44-dirty #823
Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
[<c01134f4>] (unwind_backtrace) from [<c010db2c>] (show_stack+0x20/0x24)
[<c010db2c>] (show_stack) from [<c0bd0f3c>] (dump_stack+0x94/0xa8)
[<c0bd0f3c>] (dump_stack) from [<c0151df8>] (___might_sleep+0x13c/0x174)
[<c0151df8>] (___might_sleep) from [<c0151ea0>] (__might_sleep+0x70/0xa8)
[<c0151ea0>] (__might_sleep) from [<c0bec2b8>] (mutex_lock+0x2c/0x70)
[<c0bec2b8>] (mutex_lock) from [<c0589844>] (tegra_powergate_is_powered+0x44/0xa8)
[<c0589844>] (tegra_powergate_is_powered) from [<c0581a60>] (tegra30_cpu_rail_off_ready+0x30/0x74)
[<c0581a60>] (tegra30_cpu_rail_off_ready) from [<c0122244>] (tegra30_idle_lp2+0xa0/0x108)
[<c0122244>] (tegra30_idle_lp2) from [<c0853438>] (cpuidle_enter_state+0x140/0x540)
[<c0853438>] (cpuidle_enter_state) from [<c08538a4>] (cpuidle_enter+0x40/0x4c)
[<c08538a4>] (cpuidle_enter) from [<c01595e0>] (call_cpuidle+0x30/0x48)
[<c01595e0>] (call_cpuidle) from [<c01599f8>] (do_idle+0x238/0x28c)
[<c01599f8>] (do_idle) from [<c0159d28>] (cpu_startup_entry+0x28/0x2c)
[<c0159d28>] (cpu_startup_entry) from [<c0be76c8>] (rest_init+0xd8/0xdc)
[<c0be76c8>] (rest_init) from [<c1200f50>] (start_kernel+0x41c/0x430)
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement read-only reset_reason and reset_level sysfs attributes that
can be used to query the reset reason and level at runtime.
Signed-off-by: NSandipan Patra <spatra@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Now that the Tegra xHCI driver manages the XUSB power-domains itself,
remove the code to power-up the power-domains used by the xHCI device
from the PMC driver on boot.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Cc: Li Yang <leoyang.li@nxp.com>
Cc: David Brown <david.brown@linaro.org>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Santosh Shilimkar <ssantosh@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-soc@vger.kernel.org
Acked-by: NThierry Reding <treding@nvidia.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NQiang Zhao <qiang.zhao@nxp.com>
Acked-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NRob Herring <robh@kernel.org>

Register a pinctrl device and implement get and set functions for
PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Make tegra_io_pad_set_voltage() and tegra_io_pad_get_voltage() static
and remove the prototypes from pmc.h. Remove enum tegra_io_pad_voltage
and use the defines from <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
instead.

These functions aren't used outside of the pmc driver and new use cases
should use the pinctrl interface instead.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Refactor the IO pad tables into macro tables so that they can be reused
to generate pinctrl pin descriptors. Also add a name field which is
needed by pinctrl.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement a function to query whether a pad is in deep power down mode.
This is needed by the pinctrl callbacks.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Factor out the the code to calculate the correct DPD register and bit
number for a given pad. This logic will be needed to query the status
register.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement support for the PMC_IMPL_E_33V_PWR register which replaces
PMC_PWR_DET register interface of the SoC generations preceding
Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[]
table and the AO_HV pad.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Fix child-node lookup during probe, which ended up searching the whole
device tree depth-first starting at the parent rather than just matching
on its children.

To make things worse, the parent pmc node could end up being prematurely
freed as of_find_node_by_name() drops a reference to its first argument.

Fixes: 3568df3d ("soc: tegra: Add thermal reset (thermtrip) support to PMC")
Cc: stable <stable@vger.kernel.org>     # 4.0
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: NJohan Hovold <johan@kernel.org>
Reviewed-by: NMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

With a later commit an instance of the struct device will be added to
struct genpd and with that the size of the struct tegra_powergate will
be over 1024 bytes. That generates following warning:

drivers/soc/tegra/pmc.c:579:1: warning: the frame size of 1200 bytes is larger than 1024 bytes [-Wframe-larger-than=]

Avoid such warnings by allocating the structure dynamically.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NThierry Reding <treding@nvidia.com>

As of_clk_get_parent_count() returns zero on failure, while
of_count_phandle_with_args() might return a negative error code, this
also fixes the issue of possibly using a very big number in the
allocation below.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Make use of of_reset_control_array_get_exclusive() to manage
an array of reset controllers available with the device.

Cc: Jon Hunter <jonathanh@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
[p.zabel@pengutronix.de: switch to hidden reset control array]
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

tegra_powergate_sequence_power_up() makes up a struct tegra_powergate
from scratch in order to reuse the same code as used by the generic PM
domain implementation. However, subsequent patches will need to access
the struct tegra_pmc * embedded in the powergate structure, so we need
to make sure we always pass it in.
Tested-by: NHector Martin <marcan@marcan.st>
Tested-by: NAndre Heider <a.heider@gmail.com>
Tested-by: NMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>