[why]
payload and slot number of display on dsc mst hub will be
adjusted when there is change on any display on dsc hub.
to monitor dsc enable/disable, pbn change, we need add log.

[How]
add mst_pbn to dc_dsc_config of dc_crtc_timing.
add dsc, pbn, display name within dc_core_enable_stream,
dc_core_disable_stream, dc_stream_log
Reviewed-by: NJerry Zuo <Jerry.Zuo@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NHersen Wu <hersenwu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along the following fixes:
-Fixes bugs for dsc mst hub
-Enables 29 denial itnerface by default
-Fixes dmub outbox notificatoin
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When display topology changed on DSC hub we add all crtcs with dsc support to
atomic state.
Refer to patch:"drm/amd/display: Trigger modesets on MST DSC connectors"
However the original implementation may skip crtc if the topology change
caused by unplug.
That potentially could lead to no-lightup or corruption on DSC hub after
unplug event on one of the connectors.

[How]
Update add_affected_mst_dsc_crtcs() to use old connector state
if new connector state has no crtc (undergoes modeset due to unplug)

Fixes: 44be939f ("drm/amd/display: Trigger modesets on MST DSC connectors")
Reviewed-by: NHersen Wu <hersenwu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NRoman Li <Roman.Li@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
display mapping change will involved pipe power gating on and off.
when doing this too fase, sometimes usbc will have no display.
check HW status, it is still in pipe power gating.

[how]
insert polling HW status to make sure the required state reached.
also add dal registry key handling.
Reviewed-by: NSung joon Kim <Sungjoon.Kim@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
when unplug 1 dp from dsc mst hub, atomic_check new request
dc_state only include info for the unplug dp. this will not
trigger re-compute pbn for displays still connected to hub.

[how] all displays connected to dsc hub are available in
dc->current_state, by comparing dc->current_state and new
request from atomic_chceck, it will provide info of
displays connected to hub and do pbn re-compute.
Reviewed-by: NRoman Li <Roman.Li@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NHersen Wu <hersenwu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Currently driver enables dmub outbox notification before oubox ISR is
registered. During boot scenario, sometimes dmub issues hpd outbox
message before driver registers ISR and those messages are missed.

[How]
Enable dmub outbox notification after outbox ISR is registered. Also,
restructured outbox enable code to call from dm layer and renamed APIs.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For DCN3/3.01/3.02 at least these use the fpu.

v2: squash in build fix for when DCN is not enabled (Leo)
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
In LTTPR non-transparent mode, we need
to reset the cached lane settings before performing
link training on the next PHY repeater. Otherwise,
the cached lane settings will be used for the next
clock recovery e.g. VS = MAX (3) which should not be
the case according to the DP specs. We expect to use
minimum lane settings on each clock recovery sequence.

[how]
Reset DPCD and HW lane settings on each repeater LT.
Set training pattern to 0 for the repeater that failed LT
at the proper place.
Reviewed-by: NMeenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NSung Joon Kim <sungkim@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NOliver Logush <ollogush@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes hangs on driver load with multiple displays on
DCN 2.0 parts.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215511
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1877
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1886
Fixes: ee2698cf ("drm/amd/display: Changed pipe split policy to allow for multi-display pipe split")
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

[Why]
Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will
be cleared to 0 at S3 resume.

[How]
Keep eDP Vdd on when eDP stream is already enabled.
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NZhan Liu <Zhan.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix clamping to match register field size
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...

Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be less than otg id.

e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2
so DM only registers irq_src 26,27.
This is a bug since if pipe#2 remains unfused DM never gets
otg2 pflip interrupt (irq_src=28)
That may results in gfx failure due to pflip timeout.

[How]
Register pflip interrupts per max num of otg instead of num_crtc
Signed-off-by: NRoman Li <Roman.Li@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

A number of BIOS versions have a problem with the watermarks table not
being configured properly.  This manifests as a very scary looking warning
during resume from s0i3.  This should be harmless in most cases and is well
understood, so decrease the assertion to a clearer warning about the problem.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

To align with other headers.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

To align with other headers.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes hangs on driver load with multiple displays on
DCN 2.0 parts.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215511
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1877
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1886
Fixes: ee2698cf ("drm/amd/display: Changed pipe split policy to allow for multi-display pipe split")
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The link encoder mapping could return a null one and causes system crash.

[How]
Let the mapping can get an available link encoder without endpoint
identification check.
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NMartin Tsai <martin.tsai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along the following fixes:
-fix for build failure uninitalized error
-Bug fix for DP2 using uncertified cable
-limit unbounded request to 5k
-fix DP LT sequence on EQ fail
-Bug fixes for S3/S4
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The number of lanes wasn't being reset to maximum when reducing link
rate due to an EQ failure. This could result in having fewer lanes in
the verified link capabilities, a lower maximum link bandwidth, and
fewer modes being supported.

[How]
Reset the number of lanes to max when dropping link rate due to EQ
failure during link training.
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NIlya <Ilya.Bakoulin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will
be cleared to 0 at S3 resume.

[How]
Keep eDP Vdd on when eDP stream is already enabled.
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NZhan Liu <Zhan.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
VBIOS light up eDP with 6bpc but driver use 8bpc without
disable valid stream then re-enable valid stream. Some
panels can't runtime change color depth.

[How]
Change fastboot timing validation function. Not only check
LANE_COUNT, LINK_RATE...etc
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NPaul Hsieh <paul.hsieh@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix clamping to match register field size
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Why:
When resume from sleep or hiberation, blocked MST Topology discovery might
need to be used.

How:
Added "DETECT_REASON_RESUMEFROMS3S4" to enum dc_detect_reason; use it to
require blocked MST Topology discovery.
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NBing Guo <Bing.Guo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

remove static from optc31_set_drr
Reviewed-by: NNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Unbounded requesting is unsupported on pipe split modes
and this change prevents us running into such a situation
with wide modes.
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Found when running igt@kms_atomic.

Userspace attempts to do a TEST_COMMIT when 0 streams which calls
dc_remove_stream_from_ctx. This in turn calls link_enc_unassign
which ends up modifying stream->link = NULL directly, causing the
global link_enc to be removed preventing further link activity
and future link validation from passing.

[How]
We take care of link_enc unassignment at the start of
link_enc_cfg_link_encs_assign so this call is no longer necessary.

Fixes global state from being modified while unlocked.
Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Build failure due to ‘status’ may be used uninitialized

[How]
Initialize status to LINK_TRAINING_SUCCESS
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...

Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be less than otg id.

e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2
so DM only registers irq_src 26,27.
This is a bug since if pipe#2 remains unfused DM never gets
otg2 pflip interrupt (irq_src=28)
That may results in gfx failure due to pflip timeout.

[How]
Register pflip interrupts per max num of otg instead of num_crtc
Signed-off-by: NRoman Li <Roman.Li@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The eDP link rate reported by the DP_MAX_LINK_RATE dpcd register (0xa) is
contradictory to the highest rate supported reported by
EDID (0xc = LINK_RATE_RBR2). The effects of this compounded with commit
'4a8ca46b ("drm/amd/display: Default max bpc to 16 for eDP")' results
in no display modes being found and a dark panel.

For now, simply force the maximum supported link rate for the eDP attached
2018 15" Apple Retina panels.

Additionally, we must also check the firmware revision since the device ID
reported by the DPCD is identical to that of the more capable 16,1,
incorrectly quirking it. We also use said firmware check to quirk the
refreshed 15,1 models with Vega graphics as they use a slightly newer
firmware version.
Tested-by: NAun-Ali Zaidi <admin@kodeit.net>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAun-Ali Zaidi <admin@kodeit.net>
Signed-off-by: NAditya Garg <gargaditya08@live.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

[Why]
This change causes regression, that prevents some systems
from lighting up internal displays.

[How]
Revert this patch until a new solution is ready.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Signed-off-by: NZhan Liu <Zhan.Liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

[Why]
The original latencies were causing underflow in some modes.
Resolution: 2880x1620@60p when HDR enable

[How]
1. Replace with the up-to-date watermark values based on new measurments
2. Correct the ddr_wm_table name to DDR5 on DCN31
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Signed-off-by: NPaul Hsieh <paul.hsieh@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

[Why]
There is underflow / visual corruption DCN301, for high
bandwidth MST DSC configurations such as 2x1440p144 or 2x4k60.

[How]
Use up-to-date watermark values for DCN301.
Reviewed-by: NZhan Liu <zhan.liu@amd.com>
Signed-off-by: NAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Assigning 0L to a pointer variable caused the following warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.c:71:40:
warning: Using plain integer as NULL pointer

In order to remove this warning, this commit assigns a NULL pointer to
the pointer variable that caused this issue.
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NMagali Lemes <magalilemes00@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The eDP link rate reported by the DP_MAX_LINK_RATE dpcd register (0xa) is
contradictory to the highest rate supported reported by
EDID (0xc = LINK_RATE_RBR2). The effects of this compounded with commit
'4a8ca46b ("drm/amd/display: Default max bpc to 16 for eDP")' results
in no display modes being found and a dark panel.

For now, simply force the maximum supported link rate for the eDP attached
2018 15" Apple Retina panels.

Additionally, we must also check the firmware revision since the device ID
reported by the DPCD is identical to that of the more capable 16,1,
incorrectly quirking it. We also use said firmware check to quirk the
refreshed 15,1 models with Vega graphics as they use a slightly newer
firmware version.
Tested-by: NAun-Ali Zaidi <admin@kodeit.net>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAun-Ali Zaidi <admin@kodeit.net>
Signed-off-by: NAditya Garg <gargaditya08@live.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Eliminate the follow smatch warning:
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c:2246
dp_perform_8b_10b_link_training() warn: inconsistent indenting
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DP2 sequence is triggered only if VESA certified cable is detected.

Force DP2 sequence with uncertified cable for testing purpose.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>