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  1. 28 9月, 2016 1 次提交
  3. 04 9月, 2016 1 次提交
    • W
      iio: stx104: Add IIO support for the ADC channels · 4075a283
      由 William Breathitt Gray 提交于 
      The Apex Embedded Systems STX104 features 16 channels of single-ended (8
channels of true differential) 16-bit analog input. Differential input
configuration may be selected via a physical jumper on the device.
Similarly, input polarity (unipolar/bipolar) is configured via a
physical jumper on the device.

Input gain selection is available to the user via software, thus
allowing eight possible input ranges: +-10V, +-5V, +-2.5V, +-1.25V,
0 to 10V, 0 to 5V, 0 to 2.5V, and 0 to 1.25V. Four input gain
configurations are supported: x1, x2, x4, and x8.

This ADC resolution is 16-bits (1/65536 of full scale). Analog input
samples are taken on software trigger; neither FIFO sampling nor
interrupt triggering is supported by this driver.

The Apex Embedded Systems STX104 is primarily an analog-to-digital
converter device. The STX104 IIO driver was initially placed in the DAC
directory because only the DAC portion of the STX104 was supported at
the time. Now that ADC support has been added to the STX104 IIO driver,
the driver should be moved to the more appropriate ADC directory.
Signed-off-by: NWilliam Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      4075a283
  5. 01 9月, 2016 1 次提交
  7. 29 8月, 2016 1 次提交
  9. 22 8月, 2016 1 次提交
  11. 21 8月, 2016 1 次提交
  13. 03 7月, 2016 1 次提交
  15. 13 3月, 2016 1 次提交
  17. 14 2月, 2016 1 次提交
  19. 11 2月, 2016 2 次提交
  21. 10 2月, 2016 1 次提交
  23. 16 1月, 2016 1 次提交
  25. 13 12月, 2015 2 次提交
  27. 15 11月, 2015 1 次提交
  29. 25 10月, 2015 1 次提交
  31. 24 9月, 2015 1 次提交
  33. 13 8月, 2015 1 次提交
  35. 23 5月, 2015 1 次提交
  37. 26 2月, 2015 1 次提交
  39. 30 1月, 2015 1 次提交
  41. 29 1月, 2015 1 次提交
  43. 26 10月, 2014 1 次提交
  45. 07 10月, 2014 1 次提交
  47. 07 8月, 2014 2 次提交
  49. 09 7月, 2014 1 次提交
  51. 28 6月, 2014 1 次提交
  53. 18 3月, 2014 1 次提交
  55. 17 3月, 2014 1 次提交
  57. 02 3月, 2014 1 次提交
    • L
      iio:adc: Add Xilinx XADC driver · bdc8cda1
      由 Lars-Peter Clausen 提交于 
      The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This driver
supports both interfaces and internally has a small abstraction layer that hides
the specifics of these interfaces from the main driver logic.

The ADC has a couple of internal channels which are used for voltage and
temperature monitoring of the FPGA as well as one primary and up to 16 channels
auxiliary channels for measuring external voltages. The external auxiliary
channels can either be directly connected each to one physical pin on the FPGA
or they can make use of an external multiplexer which is responsible for
multiplexing the external signals onto one pair of physical pins.

The voltage and temperature monitoring channels also have an event capability
which allows to generate a interrupt when their value falls below or raises
above a set threshold.

Buffered sampling mode is supported by the driver, but only for AXI-XADC since
the ZYNQ XADC interface does not have capabilities for supporting buffer mode
(no end-of-conversion interrupt). If buffered mode is supported the driver will
register two triggers. One "xadc-samplerate" trigger which will generate samples
with the configured samplerate. And one "xadc-convst" trigger which will
generate one sample each time the CONVST (conversion start) signal is asserted.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      bdc8cda1
  59. 01 3月, 2014 1 次提交
  61. 15 2月, 2014 1 次提交
  63. 08 9月, 2013 1 次提交
  65. 17 8月, 2013 1 次提交
    • O
      iio: twl6030-gpadc: TWL6030, TWL6032 GPADC driver · 1696f364
      由 Oleksandr Kozaruk 提交于 
      The GPADC is general purpose ADC found on TWL6030, and TWL6032 PMIC,
known also as Phoenix and PhoenixLite.

The TWL6030 and TWL6032 have GPADC with 17 and 19 channels
respectively. Some channels have current source and are used for
measuring voltage drop on resistive load for detecting battery ID
resistance, or measuring voltage drop on NTC resistors for external
temperature measurements. Some channels measure voltage, (i.e. battery
voltage), and have voltage dividers, thus, capable to scale voltage.
Some channels are dedicated for measuring die temperature.

Some channels are calibrated in 2 points, having offsets from ideal
values kept in trim registers. This is used to correct measurements.

The differences between GPADC in TWL6030 and TWL6032:
- 10 bit vs 12 bit ADC;
- 17 vs 19 channels;
- channels have different purpose(i.e. battery voltage
  channel 8 vs channel 18);
- trim values are interpreted differently.

Based on the driver patched from Balaji TK, Graeme Gregory, Ambresh K,
Girish S Ghongdemath.
Signed-off-by: NBalaji T K <balajitk@ti.com>
Signed-off-by: NGraeme Gregory <gg@slimlogic.co.uk>
Signed-off-by: NOleksandr Kozaruk <oleksandr.kozaruk@ti.com>
Signed-off-by: NJonathan Cameron <jic23@kernel.org>
      1696f364
  67. 04 8月, 2013 2 次提交
  69. 23 5月, 2013 1 次提交
  71. 16 3月, 2013 1 次提交