1. 21 12月, 2018 1 次提交
  2. 20 12月, 2018 2 次提交
  3. 18 12月, 2018 2 次提交
  4. 14 12月, 2018 2 次提交
  5. 10 12月, 2018 4 次提交
  6. 07 12月, 2018 1 次提交
    • W
      arm64: entry: Place an SB sequence following an ERET instruction · 679db708
      Will Deacon 提交于
      Some CPUs can speculate past an ERET instruction and potentially perform
      speculative accesses to memory before processing the exception return.
      Since the register state is often controlled by a lower privilege level
      at the point of an ERET, this could potentially be used as part of a
      side-channel attack.
      
      This patch emits an SB sequence after each ERET so that speculation is
      held up on exception return.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      679db708
  7. 19 10月, 2018 1 次提交
  8. 18 10月, 2018 2 次提交
  9. 03 10月, 2018 5 次提交
  10. 01 10月, 2018 9 次提交
  11. 18 9月, 2018 1 次提交
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  13. 07 9月, 2018 1 次提交
  14. 12 8月, 2018 3 次提交
  15. 26 7月, 2018 1 次提交
  16. 21 7月, 2018 4 次提交
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