1. 23 6月, 2008 2 次提交
    • S
      [ARM] add Marvell Kirkwood (88F6000) SoC support · 651c74c7
      Saeed Bishara 提交于
      The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
      Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
      a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
      interface, and IDMA/XOR engines, and depending on the model, also
      features one or two Gigabit Ethernet interfaces, two SATA II
      interfaces, one or two TWSI interfaces, one or two UARTs, a
      TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
      an SDIO interface.
      
      This patch adds supports for the Marvell DB-88F6281-BP Development
      Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
      enabling support for the PCIe interface, the USB interface, the
      ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
      UARTs, and the NAND controller.
      Signed-off-by: NSaeed Bishara <saeed@marvell.com>
      Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      651c74c7
    • L
      [ARM] add Marvell Loki (88RC8480) SoC support · 777f9beb
      Lennert Buytenhek 提交于
      The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
      core running at between 400 MHz and 1.0 GHz, and features a 64 bit
      DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
      two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
      two TWSI controllers, and IDMA/XOR engines.
      
      This patch adds support for the Marvell LB88RC8480 Development
      Board, enabling the use of the PCIe interfaces, the ethernet
      interfaces, the TWSI interfaces and the UARTs.
      Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      777f9beb
  2. 31 3月, 2008 1 次提交
  3. 28 3月, 2008 2 次提交
  4. 08 3月, 2008 1 次提交
  5. 26 1月, 2008 2 次提交
  6. 16 10月, 2007 2 次提交
    • S
      kbuild: enable 'make CPPFLAGS=...' to add additional options to CPP · 06c5040c
      Sam Ravnborg 提交于
      The variable CPPFLAGS is a wellknown variable and the usage by
      kbuild may result in unexpected behaviour.
      
      This patch replace use of CPPFLAGS with KBUILD_CPPFLAGS all over the
      tree and enabling one to use:
      make CPPFLAGS=...
      to specify additional CPP commandline options.
      
      Patch was tested on following architectures:
      alpha, arm, i386, x86_64, mips, sparc, sparc64, ia64, m68k, s390
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      06c5040c
    • S
      kbuild: enable 'make AFLAGS=...' to add additional options to AS · 222d394d
      Sam Ravnborg 提交于
      The variable AFLAGS is a wellknown variable and the usage by
      kbuild may result in unexpected behaviour.
      On top of that several people over time has asked for a way to
      pass in additional flags to gcc.
      
      This patch replace use of AFLAGS with KBUILD_AFLAGS all over
      the tree.
      
      Patch was tested on following architectures:
      alpha, arm, i386, x86_64, mips, sparc, sparc64, ia64, m68k, s390
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      222d394d
  7. 15 10月, 2007 1 次提交
    • S
      kbuild: enable 'make CFLAGS=...' to add additional options to CC · a0f97e06
      Sam Ravnborg 提交于
      The variable CFLAGS is a wellknown variable and the usage by
      kbuild may result in unexpected behaviour.
      On top of that several people over time has asked for a way to
      pass in additional flags to gcc.
      
      This patch replace use of CFLAGS with KBUILD_CFLAGS all over the
      tree and enabling one to use:
      make CFLAGS=...
      to specify additional gcc commandline options.
      
      One usecase is when trying to find gcc bugs but other
      use cases has been requested too.
      
      Patch was tested on following architectures:
      alpha, arm, i386, x86_64, mips, sparc, sparc64, ia64, m68k
      
      Test was simple to do a defconfig build, apply the patch and check
      that nothing got rebuild.
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      a0f97e06
  8. 13 10月, 2007 1 次提交
  9. 22 7月, 2007 1 次提交
  10. 12 5月, 2007 2 次提交
  11. 09 5月, 2007 1 次提交
  12. 21 2月, 2007 1 次提交
  13. 20 2月, 2007 1 次提交
  14. 18 2月, 2007 1 次提交
  15. 16 2月, 2007 1 次提交
  16. 12 2月, 2007 1 次提交
  17. 08 2月, 2007 1 次提交
  18. 08 12月, 2006 2 次提交
  19. 29 10月, 2006 1 次提交
  20. 28 9月, 2006 5 次提交
  21. 25 9月, 2006 2 次提交
  22. 28 8月, 2006 1 次提交
  23. 29 6月, 2006 1 次提交
  24. 19 6月, 2006 1 次提交
  25. 18 6月, 2006 1 次提交
  26. 09 6月, 2006 1 次提交
  27. 26 4月, 2006 1 次提交
  28. 29 3月, 2006 2 次提交
    • L
      [ARM] 3388/1: ixp23xx: add core ixp23xx support · c4713074
      Lennert Buytenhek 提交于
      Patch from Lennert Buytenhek
      
      This patch adds support for the Intel ixp23xx series of CPUs.  The
      ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
      interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
      MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
      Switch Fabric unit almost identical to the one on the ixp2400, two
      xscale (8250ish) UARTs and a bunch of other stuff.
      
      This patch adds the core ixp23xx support code, and support for the
      ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
      Espresso platforms.
      Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c4713074
    • L
      [ARM] 3377/2: add support for intel xsc3 core · 23bdf86a
      Lennert Buytenhek 提交于
      Patch from Lennert Buytenhek
      
      This patch adds support for the new XScale v3 core.  This is an
      ARMv5 ISA core with the following additions:
      
      - L2 cache
      - I/O coherency support (on select chipsets)
      - Low-Locality Reference cache attributes (replaces mini-cache)
      - Supersections (v6 compatible)
      - 36-bit addressing (v6 compatible)
      - Single instruction cache line clean/invalidate
      - LRU cache replacement (vs round-robin)
      
      I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
      cores have separate errata and have to handle things like L2, so it
      is simpler to keep it separate.
      
      L2 cache support is currently a build option because the L2 enable
      bit must be set before we enable the MMU and there is no easy way to
      capture command line parameters at this point.
      
      There are still optimizations that can be done such as using LLR for
      copypage (in theory using the exisiting mini-cache code) but those
      can be addressed down the road.
      Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      23bdf86a