- 14 8月, 2014 1 次提交
-
-
由 Max Filippov 提交于
Existing clear_user_page and copy_user_page cannot be used with highmem because they calculate physical page address from its virtual address and do it incorrectly in case of high memory page mapped with kmap_atomic. Also kmap is not needed, as most likely userspace mapping color would be different from the kmapped color. Provide clear_user_highpage and copy_user_highpage functions that determine if temporary mapping is needed for the pages. Move most of the logic of the former clear_user_page and copy_user_page to xtensa/mm/cache.c only leaving temporary mapping setup, invalidation and clearing/copying in the xtensa/mm/misc.S. Rename these functions to clear_page_alias and copy_page_alias. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
-
- 07 4月, 2014 1 次提交
-
-
由 Max Filippov 提交于
Introduce fixmap area just below the vmalloc region. Use it for atomic mapping of high memory pages. High memory on cores with cache aliasing is not supported and is still to be implemented. Fail build for such configurations for now. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
-
- 15 1月, 2014 1 次提交
-
-
由 Max Filippov 提交于
This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NChris Zankel <chris@zankel.net>
-
- 19 12月, 2012 1 次提交
-
-
由 Chris Zankel 提交于
Remove heading and trailing spaces, trim trailing lines, and wrap lines that are longer than 80 characters. Signed-off-by: NChris Zankel <chris@zankel.net>
-
- 21 2月, 2010 1 次提交
-
-
由 Russell King 提交于
On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 14 2月, 2008 2 次提交
-
-
由 Chris Zankel 提交于
The TLB entry for the user address doesn't exist at the time we want to flush the caches, so use the page address. Note that processor configurations with cache-aliasing issues are treated separately. Signed-off-by: NChris Zankel <chris@zankel.net>
-
由 Chris Zankel 提交于
Signed-off-by: NLucas Woods <woodzy@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NChristian Zankel <chris@zankel.net>
-
- 28 8月, 2007 1 次提交
-
-
由 Chris Zankel 提交于
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: NChris Zankel <chris@zankel.net>
-