1. 28 6月, 2018 1 次提交
    • J
      serial: max310x: Check the clock readiness · 4cf9a888
      Jan Kundrát 提交于
      This chip has a diagnostics status bit informing about the state and
      stability of the clock subsystem. According to the datasheet (STSint
      register, bit 5, ClockReady), this bit works with the crystal
      oscillator, but even without the PLL. Therefore:
      
      - ensure that the clock check is done even when PLL is not active
      - warn when the chip thinks that the clock is not ready yet
      
      There are HW features which would let us wait asynchronously (there's a
      maskable IRQ for that bit), but I think that even this simple check is a
      net improvement. It would have saved me two days of debugging :).
      Signed-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4cf9a888
  2. 28 2月, 2018 1 次提交
    • J
      gpio: serial: max310x: Use HW type for gpio_chip's label · 1a9ab351
      Jan Kundrát 提交于
      Some debugging tools (/sys/kernel/debug/gpio, `lsgpio`) use the
      gpio_chip's label for displaying an additional context. Right now, the
      information duplicates stuff which is already available from the
      parent's device. This is how e.g. `lsgpio`'s output looks like:
      
        GPIO chip: gpiochip2, "spi1.2", 16 GPIO lines
      
      Comparing the output of other GPIO expanders that I have available:
      
        gpiochip4: GPIOs 464-479, parent: spi/spi1.1, mcp23s17, can sleep:
        gpiochip5: GPIOs 448-463, parent: i2c/0-0020, pca9555, can sleep:
        gpiochip2: GPIOs 496-511, parent: spi/spi1.2, spi1.2, can sleep:
      
      This patch ensures that the type of the real HW device is shown instead
      of duplicating the SPI path:
      
        gpiochip2: GPIOs 496-511, parent: spi/spi1.2, MAX14830, can sleep:
      Signed-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      1a9ab351
  3. 10 1月, 2018 1 次提交
  4. 19 12月, 2017 5 次提交
    • J
      serial: max310x: Reduce RX work starvation · 22587612
      Jan Kundrát 提交于
      Prior to this patch, the code would happily trigger TX on some ports
      before having a chance of reading the RX buffer from the rest of them.
      When no flow control was used, this led to RX buffer overruns and
      therefore lost data under certain circumstances.
      
      I was able to reproduce this with MAX14830 (that's a quad channel one)
      and a simple daisy-chain of RX and TX ports on the eval board:
      
      - TX0 -> RX1
      - TX1 -> RX2
      - TX2 -> RX3
      - TX3 -> RX0
      
      I was testing this by transferring 2MB of data at 115200 baud via each
      port. I used a Solidrun Clearfog Base (Armada 388) which was talking to
      the UART over an SPI bus clocked at 26MHz (the chip's maximum). Without
      this patch, I would always get a "Possible RX FIFO overrun" in dmesg,
      and fewer-than-expected amount of bytes received over ttyMAX0. Results
      on ttyMAX{1,2,3} tended to be correct all the time, even without the
      previous patches in this series and with PIO SPI transfers ("indirect
      mode" as the Marvell datasheet calls it), so I assume that heavy
      congestion is needed in order to reproduce this.
      
      A drawback of this patch is that the throughput gets reduced "a bit".
      Previously, a 115200 baud resulted in about 11.2kBps throughput as
      reported by a simple `pv`. With this patch, the throughput of four
      parallel streams is roughly 7kBps each, and 9kBps for three streams.
      There is no slowdown for one or two parallel streams.
      
      Situation is worse if bytes are being read one-by-one (such as if the
      userspace wants to perform parity/framing/break checking) and therefore
      without the batched reads.
      
      With just this patch and no other modifications on top of 4.14, I was
      only getting roughly 3.6kBps with four parallel streams. The
      single-stream performance was the same, and I was seeing about 7.2kBps
      with two parallel streams. `perf top` said that a substantial amount of
      time was spent in `finish_task_switch`, `_raw_spin_unlock_irqrestore`
      and `__timer_delay`.
      Signed-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      22587612
    • J
      serial: max310x: Use batched reads when reasonably safe · 2b4bac48
      Jan Kundrát 提交于
      The hardware has a 128 byte RX FIFO buffer for each independent UART.
      Previously, the code was always reading that byte-by-byte via
      independent SPI transactions and the associated overhead. In practice,
      this led to up to eight bytes over SPI for just one byte in the UART's
      RX FIFO:
      
      - reading the global IRQ register (two bytes, one for command, the other
      for data)
      - reading one UART's ISR (again two bytes)
      - reading the byte count (two bytes yet again)
      - finally, reading one byte of the FIFO via another two-byte transaction
      
      We cannot always use a batched read. If the TTY is set to intercept
      break conditions or report framing or parity errors, then it is required
      to check the Line Status Register (LSR) for each byte which is read from
      the RX FIFO. The documentation does not show a way of doing that in a
      single SPI transaction; registers 0x00 and 0x04 are separate.
      
      In my testing, this is no silver bullet. I was feeding 2MB of random
      data over four daisy-chaned UARTs of MAX14830, and this is the
      distribution that I was getting:
      
      - R <= 1: 7437322
      - R <= 2: 162093
      - R <= 4: 4093
      - R <= 8: 4196
      - R <= 16: 645
      - R <= 32: 165
      - R <= 64: 58
      - R <= 128: 0
      
      For a reference, batching the write operations works much better:
      
      - W <= 1: 2664
      - W <= 2: 1305
      - W <= 4: 627
      - W <= 8: 371
      - W <= 16: 121
      - W <= 32: 68
      - W <= 64: 33
      - W <= 128: 63139
      
      That's probably because this HW/SW combination (Clearfog Base, Armada
      388) is probably "good enough" to react to the chip's IRQ "fast enough"
      most of the time. Still, I was getting RX overruns every now and then.
      In future, I plan to improve this by letting the RX FIFO be filled a
      little more (the chip has support for that and also for a "stale
      timeout" to prevent additional starvation).
      Signed-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      2b4bac48
    • J
      serial: max310x: use a batch write op for UART transmit · d584b65c
      Jan Kundrát 提交于
      The transmit register supports batched writes. The key is simply to keep
      sending additional bytes up to the FIFO size in the same SPI
      transaction with the CS pin still being held low.
      
      This duplicates the regmap infrastructure to a certain extent. There are
      some provisions for multiple writes in there, but there does not appear
      to be any support for those writes which are destined to the *same*
      register (and also no standard for SPI bus transfers of these, anyway).
      
      This patch does not solve every case (if the UART xmit circular buffer
      wraps around, we're still doing two SPI transactions), but at least
      it's not one-byte-per-transaction anymore.
      
      This change does not touch the receive path at this time. Doing that in
      the generic case appears to be impossible in the general case, because
      the chips' status register contains data about the *current* byte in the
      HW's Rx FIFO. We cannot read these two registers in one go,
      unfortunately.
      Signed-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      d584b65c
    • J
      serial: max310x: Support IRQ sharing with other devices · 78be70c8
      Jan Kundrát 提交于
      According to my chip's datasheet [1], the IRQ output is an open
      collector pin which is suitable for sharing with other chips. The chip
      also has a register which indicates which UART performed a change and
      the driver checks that register already, so we have everything what is
      needed to effectively share the IRQ GPIO.
      
      [1] https://datasheets.maximintegrated.com/en/ds/MAX14830.pdfSigned-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      78be70c8
    • J
      serial: max310x: Do not hard-code the IRQ type · bceb4839
      Jan Kundrát 提交于
      As suggested by Russell King, a driver should not really care about bits
      such as the interrupt polarity or whether it is edge- or level-
      triggered. The reasons for that include:
      
      - an upstream IRQ controller which cannot support edge- or
      level-triggered interrupts,
      - board design with a built-in inverter
      
      The interrupt type is being already specified by the Device Tree,
      anyway. Other drivers (gpio/gpio-tc3589x.c for example) already work in
      this way, delegating the proper IRQ line setup to the DT and not
      specifying anything by hand.
      
      Also, there's no reason to have the IRQ flags split between two places.
      The SPI probing is the only entry point anyway.
      Signed-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      bceb4839
  5. 16 12月, 2017 1 次提交
    • J
      serial: max310x: Fix invalid memory access during GPIO init · 38d5583f
      Jan Kundrát 提交于
      The `max310x_spi_probe` function attempted to setup the GPIO bits before
      the corresponding structs for each serial port were initialized. If the
      DTS file specified a GPIO hog, this led to a crash because the GPIO
      stack ended up calling `max310x_gpio_direction_output` which referenced
      uninitialized memory:
      
       [<c04598c0>] (max310x_gpio_direction_output) from [<c03f5a2c>] (_gpiod_direction_output_raw+0x94/0x2d4)
       [<c03f5a2c>] (_gpiod_direction_output_raw) from [<c03f991c>] (gpiod_hog+0x6c/0x154)
       [<c03f991c>] (gpiod_hog) from [<c03fa2d8>] (of_gpiochip_add+0x28c/0x444)
       [<c03fa2d8>] (of_gpiochip_add) from [<c03f6b2c>] (gpiochip_add_data+0x4f8/0x760)
       [<c03f6b2c>] (gpiochip_add_data) from [<c03f6dd4>] (devm_gpiochip_add_data+0x40/0x7c)
       [<c03f6dd4>] (devm_gpiochip_add_data) from [<c0459fec>] (max310x_spi_probe+0x530/0x894)
       [<c0459fec>] (max310x_spi_probe) from [<c0503294>] (spi_drv_probe+0x7c/0xac)
       [<c0503294>] (spi_drv_probe) from [<c046628c>] (driver_probe_device+0x234/0x2e8)
       [<c046628c>] (driver_probe_device) from [<c0464890>] (bus_for_each_drv+0x60/0x94)
       [<c0464890>] (bus_for_each_drv) from [<c0465f78>] (__device_attach+0xb0/0x114)
       [<c0465f78>] (__device_attach) from [<c0465548>] (bus_probe_device+0x84/0x8c)
       [<c0465548>] (bus_probe_device) from [<c0463a00>] (device_add+0x3f4/0x580)
       [<c0463a00>] (device_add) from [<c0504164>] (spi_add_device+0x9c/0x134)
       [<c0504164>] (spi_add_device) from [<c0504c18>] (spi_register_controller+0x484/0x910)
       [<c0504c18>] (spi_register_controller) from [<c0506ee0>] (orion_spi_probe+0x2f4/0x3b4)
       [<c0506ee0>] (orion_spi_probe) from [<c0467dac>] (platform_drv_probe+0x50/0xb0)
       [<c0467dac>] (platform_drv_probe) from [<c046628c>] (driver_probe_device+0x234/0x2e8)
       [<c046628c>] (driver_probe_device) from [<c04663f8>] (__driver_attach+0xb8/0xbc)
       [<c04663f8>] (__driver_attach) from [<c04647e8>] (bus_for_each_dev+0x68/0x9c)
       [<c04647e8>] (bus_for_each_dev) from [<c046574c>] (bus_add_driver+0x104/0x210)
       [<c046574c>] (bus_add_driver) from [<c0466f14>] (driver_register+0x78/0xf4)
       [<c0466f14>] (driver_register) from [<c0101bdc>] (do_one_initcall+0x44/0x168)
       [<c0101bdc>] (do_one_initcall) from [<c0a00dc0>] (kernel_init_freeable+0x140/0x1cc)
       [<c0a00dc0>] (kernel_init_freeable) from [<c078c590>] (kernel_init+0x8/0x108)
       [<c078c590>] (kernel_init) from [<c0107a50>] (ret_from_fork+0x14/0x24)
      
      This can be easily fixed by moving the corresponding code below. And
      because the UARTs are already there by the time we reach this point, the
      `goto` needs changing so that more stuff is freed. (I have not tested
      this error path.)
      Signed-off-by: NJan Kundrát <jan.kundrat@cesnet.cz>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      38d5583f
  6. 08 11月, 2017 2 次提交
    • G
      tty: serial: Remove redundant license text · 4793f2eb
      Greg Kroah-Hartman 提交于
      Now that the SPDX tag is in all tty files, that identifies the license
      in a specific and legally-defined manner.  So the extra GPL text wording
      can be removed as it is no longer needed at all.
      
      This is done on a quest to remove the 700+ different ways that files in
      the kernel describe the GPL license text.  And there's unneeded stuff
      like the address (sometimes incorrect) for the FSF which is never
      needed.
      
      No copyright headers or other non-license-description text was removed.
      
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Eric Anholt <eric@anholt.net>
      Cc: Stefan Wahren <stefan.wahren@i2se.com>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Ray Jui <rjui@broadcom.com>
      Cc: Scott Branden <sbranden@broadcom.com>
      Cc: bcm-kernel-feedback-list@broadcom.com
      Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Joachim Eastwood <manabian@gmail.com>
      Cc: Matthias Brugger <matthias.bgg@gmail.com>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: Tobias Klauser <tklauser@distanz.ch>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Cc: Richard Genoud <richard.genoud@gmail.com>
      Cc: Alexander Shiyan <shc_work@mail.ru>
      Cc: Baruch Siach <baruch@tkos.co.il>
      Cc: Pat Gefre <pfg@sgi.com>
      Cc: "Guilherme G. Piccoli" <gpiccoli@linux.vnet.ibm.com>
      Cc: Jason Wessel <jason.wessel@windriver.com>
      Cc: Vladimir Zapolskiy <vz@mleia.com>
      Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
      Cc: Carlo Caione <carlo@caione.org>
      Cc: Kevin Hilman <khilman@baylibre.com>
      Cc: Liviu Dudau <liviu.dudau@arm.com>
      Cc: Sudeep Holla <sudeep.holla@arm.com>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Andy Gross <andy.gross@linaro.org>
      Cc: David Brown <david.brown@linaro.org>
      Cc: "Andreas Färber" <afaerber@suse.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Kevin Cernekee <cernekee@gmail.com>
      Cc: Laxman Dewangan <ldewangan@nvidia.com>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Jonathan Hunter <jonathanh@nvidia.com>
      Cc: Barry Song <baohua@kernel.org>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Chris Metcalf <cmetcalf@mellanox.com>
      Cc: Peter Korsgaard <jacmet@sunsite.dk>
      Cc: Timur Tabi <timur@tabi.org>
      Cc: Tony Prisk <linux@prisktech.co.nz>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4793f2eb
    • G
      tty: add SPDX identifiers to all remaining files in drivers/tty/ · e3b3d0f5
      Greg Kroah-Hartman 提交于
      It's good to have SPDX identifiers in all files to make it easier to
      audit the kernel tree for correct licenses.
      
      Update the drivers/tty files files with the correct SPDX license
      identifier based on the license text in the file itself.  The SPDX
      identifier is a legally binding shorthand, which can be used instead of
      the full boiler plate text.
      
      This work is based on a script and data from Thomas Gleixner, Philippe
      Ombredanne, and Kate Stewart.
      
      Cc: Jiri Slaby <jslaby@suse.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Chris Metcalf <cmetcalf@mellanox.com>
      Cc: Jiri Kosina <jikos@kernel.org>
      Cc: David Sterba <dsterba@suse.com>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: Rob Herring <robh@kernel.org>
      Cc: Eric Anholt <eric@anholt.net>
      Cc: Stefan Wahren <stefan.wahren@i2se.com>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Ray Jui <rjui@broadcom.com>
      Cc: Scott Branden <sbranden@broadcom.com>
      Cc: bcm-kernel-feedback-list@broadcom.com
      Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Joachim Eastwood <manabian@gmail.com>
      Cc: Matthias Brugger <matthias.bgg@gmail.com>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: Tobias Klauser <tklauser@distanz.ch>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Cc: Richard Genoud <richard.genoud@gmail.com>
      Cc: Alexander Shiyan <shc_work@mail.ru>
      Cc: Baruch Siach <baruch@tkos.co.il>
      Cc: "Maciej W. Rozycki" <macro@linux-mips.org>
      Cc: "Uwe Kleine-König" <kernel@pengutronix.de>
      Cc: Pat Gefre <pfg@sgi.com>
      Cc: "Guilherme G. Piccoli" <gpiccoli@linux.vnet.ibm.com>
      Cc: Jason Wessel <jason.wessel@windriver.com>
      Cc: Vladimir Zapolskiy <vz@mleia.com>
      Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
      Cc: Carlo Caione <carlo@caione.org>
      Cc: Kevin Hilman <khilman@baylibre.com>
      Cc: Liviu Dudau <liviu.dudau@arm.com>
      Cc: Sudeep Holla <sudeep.holla@arm.com>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Andy Gross <andy.gross@linaro.org>
      Cc: David Brown <david.brown@linaro.org>
      Cc: "Andreas Färber" <afaerber@suse.de>
      Cc: Kevin Cernekee <cernekee@gmail.com>
      Cc: Laxman Dewangan <ldewangan@nvidia.com>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Jonathan Hunter <jonathanh@nvidia.com>
      Cc: Barry Song <baohua@kernel.org>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Peter Korsgaard <jacmet@sunsite.dk>
      Cc: Timur Tabi <timur@tabi.org>
      Cc: Tony Prisk <linux@prisktech.co.nz>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Kate Stewart <kstewart@linuxfoundation.org>
      Cc: Philippe Ombredanne <pombredanne@nexb.com>
      Cc: Jiri Slaby <jslaby@suse.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      e3b3d0f5
  7. 12 1月, 2017 1 次提交
  8. 15 9月, 2016 1 次提交
  9. 26 6月, 2016 6 次提交
  10. 26 4月, 2016 1 次提交
  11. 19 11月, 2015 1 次提交
    • L
      gpio: change member .dev to .parent · 58383c78
      Linus Walleij 提交于
      The name .dev in a struct is normally reserved for a struct device
      that is let us say a superclass to the thing described by the struct.
      struct gpio_chip stands out by confusingly using a struct device *dev
      to point to the parent device (such as a platform_device) that
      represents the hardware. As we want to give gpio_chip:s real devices,
      this is not working. We need to rename this member to parent.
      
      This was done by two coccinelle scripts, I guess it is possible to
      combine them into one, but I don't know such stuff. They look like
      this:
      
      @@
      struct gpio_chip *var;
      @@
      -var->dev
      +var->parent
      
      and:
      
      @@
      struct gpio_chip var;
      @@
      -var.dev
      +var.parent
      
      and:
      
      @@
      struct bgpio_chip *var;
      @@
      -var->gc.dev
      +var->gc.parent
      
      Plus a few instances of bgpio that I couldn't figure out how
      to teach Coccinelle to rewrite.
      
      This patch hits all over the place, but I *strongly* prefer this
      solution to any piecemal approaches that just exercise patch
      mechanics all over the place. It mainly hits drivers/gpio and
      drivers/pinctrl which is my own backyard anyway.
      
      Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
      Cc: Rafał Miłecki <zajec5@gmail.com>
      Cc: Richard Purdie <rpurdie@rpsys.net>
      Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
      Cc: Alek Du <alek.du@intel.com>
      Cc: Jaroslav Kysela <perex@perex.cz>
      Cc: Takashi Iwai <tiwai@suse.com>
      Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
      Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      Acked-by: NLee Jones <lee.jones@linaro.org>
      Acked-by: NJiri Kosina <jkosina@suse.cz>
      Acked-by: NHans-Christian Egtvedt <egtvedt@samfundet.no>
      Acked-by: NJacek Anaszewski <j.anaszewski@samsung.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      58383c78
  12. 28 10月, 2015 1 次提交
  13. 07 11月, 2014 1 次提交
  14. 06 11月, 2014 2 次提交
  15. 19 9月, 2014 1 次提交
  16. 10 7月, 2014 1 次提交
  17. 20 6月, 2014 1 次提交
    • P
      serial: Fix IGNBRK handling · ef8b9ddc
      Peter Hurley 提交于
      If IGNBRK is set without either BRKINT or PARMRK set, some uart
      drivers send a 0x00 byte for BREAK without the TTYBREAK flag to the
      line discipline, when it should send either nothing or the TTYBREAK flag
      set. This happens because the read_status_mask masks out the BI
      condition, which uart_insert_char() then interprets as a normal 0x00 byte.
      
      SUS v3 is clear regarding the meaning of IGNBRK; Section 11.2.2, General
      Terminal Interface - Input Modes, states:
        "If IGNBRK is set, a break condition detected on input shall be ignored;
         that is, not put on the input queue and therefore not read by any
         process."
      
      Fix read_status_mask to include the BI bit if IGNBRK is set; the
      lsr status retains the BI bit if a BREAK is recv'd, which is
      subsequently ignored in uart_insert_char() when masked with the
      ignore_status_mask.
      
      Affected drivers:
      8250 - all
      serial_txx9
      mfd
      amba-pl010
      amba-pl011
      atmel_serial
      bfin_uart
      dz
      ip22zilog
      max310x
      mxs-auart
      netx-serial
      pnx8xxx_uart
      pxa
      sb1250-duart
      sccnxp
      serial_ks8695
      sirfsoc_uart
      st-asc
      vr41xx_siu
      zs
      sunzilog
      fsl_lpuart
      sunsab
      ucc_uart
      bcm63xx_uart
      sunsu
      efm32-uart
      pmac_zilog
      mpsc
      msm_serial
      m32r_sio
      
      Unaffected drivers:
      omap-serial
      rp2
      sa1100
      imx
      icom
      
      Annotated for fixes:
      altera_uart
      mcf
      
      Drivers without break detection:
      21285
      xilinx-uartps
      altera_jtaguart
      apbuart
      arc-uart
      clps711x
      max3100
      uartlite
      msm_serial_hs
      nwpserial
      lantiq
      vt8500_serial
      
      Unknown:
      samsung
      mpc52xx_uart
      bfin_sport_uart
      cpm_uart/core
      
      Fixes: Bugzilla #71651, '8250_core.c incorrectly handles IGNBRK flag'
      Reported-by: NIvan <athlon_@mail.ru>
      Signed-off-by: NPeter Hurley <peter@hurleysoftware.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      ef8b9ddc
  18. 18 3月, 2014 1 次提交
  19. 16 2月, 2014 1 次提交
  20. 14 2月, 2014 10 次提交