Rather than having SoCs work around L2C erratum themselves, move them
into core code.  This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort.  Platforms normally have to call
firmware to work around this.  Provide a hook for them to intercept
any L2C secure register write.

l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Move the way size calculation data (base of way size) out of the
switch statement into the provided initialisation data.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than decoding this from the ID register, store it in the
l2c_init_data structure.  This simplifies things some more, and
allows us to better provide further details as to how we're
driving the cache.  We print the cache ID value anyway should we
need to precisely identify the cache hardware.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of the
old (and buggy) l2x0_*-based operations structure.

This is also the last reference to:
- l2x0_clean_line()
- l2x0_inv_line()
- l2x0_flush_line()
- l2x0_flush_all()
- l2x0_clean_all()
- l2x0_inv_all()
- l2x0_inv_range()
- l2x0_clean_range()
- l2x0_flush_range()
- l2x0_enable()
- l2x0_resume()
so kill those functions too.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later.  These
require no errata workarounds, and so we can directly call the l2c210
functions from their methods.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks to protect all operations, and we have to wait for every
operation to complete.

Should a second operation be attempted while a previous operation
is in progress, the response will be an imprecise abort.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Where no errata affect the L2C-310 handlers, they are functionally
equivalent to L2C-210.  Re-use the L2C-210 handlers for the L2C-310
part.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations structure.
This allows us to sensibly contain the erratum code in one place
without affecting other locations/implemetations.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure.  This allows us to sensibly
contain the erratum code in one place without affecting other
locations or implementations.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add L2C-210 specific cache operation handlers.  These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require any workarounds.  We avoid using the way operations during
normal operation, which means we can avoid locking: the only time
we use the way operations are during initialisation, and when
disabling the cache.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Move the pl310_set_debug() into the l2c-310 code area, and don't hide
it with ifdefs.  Rename it to l2c310_set_debug().
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The l2x0 unlocking code is only called from l2x0_enable() now, so move
the logic entirely into that function and simplify it.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name.  Use a local cached copy of the l2x0_base
virtual address, and also realise that many of the resume function
tails are the same as the enable functions, so make a call to the
enable function instead of duplicating that code.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementations to be any different
from the OF implementations.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Make one of them purely "English", and the other purely technical.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify.  This
helps to localise the quirks to those implementations which require
them.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead.  While here, clean
up that code and comments a little.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value.  This allows us to
avoid invoking the platforms secure monitor code unnecessarily.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock
registers.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time.  This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.

This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.

Organise it according to implementation.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

There's no reason this functionality should be specific to DT, so move
it into the common initialisation function.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Pass the iomem address into this function so we don't have to keep
accessing it from a global.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than having a boolean and other tricks to disable some bits of
l2x0_init(), split this function into two parts: a common part shared
between OF and non-OF, and the non-OF part.

The common part can take a block of function pointers, and the cache
ID (to cope with Aurora's DT specified ID.)  Eliminate the redundant
setting of l2x0_base in the OF case, moving it to the non-OF init
function.

This allows us to localise the OF-specific initialisation handling
from the non-OF handling.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The revision namespace is specific to the L2 cache part, so don't name
these with generic identifiers, use a part specific identifier.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

cache_wait_way() is actually used to wait for a particular mask to
report clear; it's not really got much to do with cache ways at all.
Indeed, it gets used to wait for the C bit to clear on older caches.
Rename this with a more generic function name which better reflects
its purpose: l2c_wait_mask().
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide a generic helper function for way based operations.  These are
always background operations, and thus have to be waited for before a
new operation is commenced.  This helper extracts that requirement from
several locations in the code.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Split the cache unlock code out of l2x0_unlock().  We want to be able
to re-use this functionality later.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide a generic function which always calls the set_debug method.
This will be used later in the series as some work-arounds require
that the debug register be written.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rename a few things to help distinguish their function(s):
 l2x0_of_data -> l2c_init_data
 setup -> of_parse
 add of_ prefix to OF specific data
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Remove NULL initialisers, make these all __initconst structures, and
order their members in the same order as the structure declaration.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Make it easier to declare L2 cache controller DT IDs by using a macro.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

No one ever calls this function anywhere in the kernel, so let's
completely remove it from the outer cache API and turn it into an
internal-only thing.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

[ this is a follow-up to this discussion:
http://archive.arm.linux.org.uk/lurker/message/20130730.230827.a1ceb12a.en.html ]
This patchset renames all uses of "bcm," name bindings to
"brcm," as they were done prior to knowing that brcm had
already been standardized as Broadcom vendor prefix
(in Documentation/devicetree/bindings/vendor-prefixes.txt).
This will not cause any churn on devices because none of
these bindings have made it into production yet.
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NChristian Daudt <csd@broadcom.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Currently we have the following output from cache-l2x0:

l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1048576 B

Using kB for the cache size can improve readability a bit:

l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1024 kB

While at it use pr_info.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

writel_relaxed and spin_unlock are both store operations, so we only
need to enforce store ordering in the dsb.
Signed-off-by: NWill Deacon <will.deacon@arm.com>

Rev A2 SoCs have an unorthodox memory re-mapping and this needs
to be reflected in the cache operations.
This patch adds new outer cache functions for the l2x0 driver
to support this SoC revision. It also adds a new compatible
value for the cache to enable this functionality.

Updates from V1:
- remove section 1 altogether and note that in comments
- simplify section selection caused by section 1 removal
- BUG_ON just in case section 1 shows up
Signed-off-by: NChristian Daudt <csd@broadcom.com>
Reviewed-by: NWill Deacon <will.deacon@arm.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>