1. 27 7月, 2017 1 次提交
  2. 15 7月, 2017 1 次提交
    • S
      drm: handle HDMI 2.0 VICs in AVI info-frames · 0c1f528c
      Shashank Sharma 提交于
      HDMI 1.4b support the CEA video modes as per range of CEA-861-D (VIC 1-64).
      For any other mode, the VIC filed in AVI infoframes should be 0.
      HDMI 2.0 sinks, support video modes range as per CEA-861-F spec, which is
      extended to (VIC 1-107).
      
      This patch adds a bool input variable, which indicates if the connected
      sink is a HDMI 2.0 sink or not. This will make sure that we don't pass a
      HDMI 2.0 VIC to a HDMI 1.4 sink.
      
      This patch touches all drm drivers, who are callers of this function
      drm_hdmi_avi_infoframe_from_display_mode but to make sure there is
      no change in current behavior, is_hdmi2 is kept as false.
      
      In case of I915 driver, this patch:
      - checks if the connected display is HDMI 2.0.
      - HDMI infoframes carry one of this two type of information:
      	- VIC for 4K modes for HDMI 1.4 sinks
      	- S3D information for S3D modes
        As CEA-861-F has already defined VICs for 4K videomodes, this
        patch doesn't allow sending HDMI infoframes for HDMI 2.0 sinks,
        until the mode is 3D.
      
      Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
      Cc: Jose Abreu <jose.abreu@synopsys.com>
      Cc: Andrzej Hajda <a.hajda@samsung.com>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      
      PS: This patch touches a few lines in few files, which were
      already above 80 char, so checkpatch gives 80 char warning again.
      - gpu/drm/omapdrm/omap_encoder.c
      - gpu/drm/i915/intel_sdvo.c
      
      V2: Rebase, Added r-b from Andrzej
      V3: Addressed review comment from Ville:
      	- Do not send VICs in both AVI-IF and HDMI-IF
      	  send only one of it.
      V4: Rebase
      V5: Added r-b from Neil.
          Addressed review comments from Ville
          - Do not block HDMI vendor IF, instead check for VIC while
            handling AVI infoframes
      V6: Rebase
      V7: Rebase
      Reviewed-by: NAndrzej Hajda <a.hajda@samsung.com>
      Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
      Signed-off-by: NShashank Sharma <shashank.sharma@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1499960000-9232-2-git-send-email-shashank.sharma@intel.comSigned-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      0c1f528c
  3. 23 6月, 2017 1 次提交
  4. 16 6月, 2017 1 次提交
  5. 30 5月, 2017 2 次提交
  6. 10 5月, 2017 1 次提交
  7. 08 5月, 2017 1 次提交
  8. 27 2月, 2017 1 次提交
  9. 08 12月, 2016 1 次提交
  10. 25 11月, 2016 1 次提交
  11. 17 11月, 2016 1 次提交
  12. 01 11月, 2016 2 次提交
  13. 14 10月, 2016 2 次提交
  14. 13 10月, 2016 1 次提交
  15. 22 9月, 2016 1 次提交
  16. 23 8月, 2016 3 次提交
  17. 22 8月, 2016 1 次提交
  18. 05 7月, 2016 1 次提交
  19. 04 7月, 2016 1 次提交
  20. 24 6月, 2016 3 次提交
  21. 19 6月, 2016 1 次提交
  22. 11 6月, 2016 1 次提交
  23. 30 5月, 2016 1 次提交
  24. 29 3月, 2016 1 次提交
  25. 01 3月, 2016 1 次提交
  26. 11 2月, 2016 1 次提交
  27. 11 12月, 2015 1 次提交
  28. 18 11月, 2015 2 次提交
    • V
      drm/i915: Type safe register read/write · f0f59a00
      Ville Syrjälä 提交于
      Make I915_READ and I915_WRITE more type safe by wrapping the register
      offset in a struct. This should eliminate most of the fumbles we've had
      with misplaced parens.
      
      This only takes care of normal mmio registers. We could extend the idea
      to other register types and define each with its own struct. That way
      you wouldn't be able to accidentally pass the wrong thing to a specific
      register access function.
      
      The gpio_reg setup is probably the ugliest thing left. But I figure I'd
      just leave it for now, and wait for some divine inspiration to strike
      before making it nice.
      
      As for the generated code, it's actually a bit better sometimes. Eg.
      looking at i915_irq_handler(), we can see the following change:
        lea    0x70024(%rdx,%rax,1),%r9d
        mov    $0x1,%edx
      - movslq %r9d,%r9
      - mov    %r9,%rsi
      - mov    %r9,-0x58(%rbp)
      - callq  *0xd8(%rbx)
      + mov    %r9d,%esi
      + mov    %r9d,-0x48(%rbp)
       callq  *0xd8(%rbx)
      
      So previously gcc thought the register offset might be signed and
      decided to sign extend it, just in case. The rest appears to be
      mostly just minor shuffling of instructions.
      
      v2: i915_mmio_reg_{offset,equal,valid}() helpers added
          s/_REG/_MMIO/ in the register defines
          mo more switch statements left to worry about
          ring_emit stuff got sorted in a prep patch
          cmd parser, lrc context and w/a batch buildup also in prep patch
          vgpu stuff cleaned up and moved to a prep patch
          all other unrelated changes split out
      v3: Rebased due to BXT DSI/BLC, MOCS, etc.
      v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
      f0f59a00
    • V
      drm/i915: s/is_sdvob/enum port/ · 2a5c0832
      Ville Syrjälä 提交于
      Replace the is_sdvob bool and some sdvo_reg checks with enum port. This
      makes the SDVO code look more modern, and gets rid of explicit register
      offset checks in the code which will hamper register type checking.
      
      v2: Add assert_sdvo_port_valid() (Chris)
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1446838199-3666-1-git-send-email-ville.syrjala@linux.intel.com
      2a5c0832
  29. 10 11月, 2015 1 次提交
  30. 09 10月, 2015 1 次提交
  31. 06 10月, 2015 1 次提交
  32. 30 9月, 2015 1 次提交