1. 11 5月, 2020 1 次提交
    • A
      net: phy: Add cable test support to state machine · a68a8138
      Andrew Lunn 提交于
      Running a cable test is desruptive to normal operation of the PHY and
      can take a 5 to 10 seconds to complete. The RTNL lock cannot be held
      for this amount of time, and add a new state to the state machine for
      running a cable test.
      
      The driver is expected to implement two functions. The first is used
      to start a cable test. Once the test has started, it should return.
      
      The second function is called once per second, or on interrupt to
      check if the cable test is complete, and to allow the PHY to report
      the status.
      
      v2:
      Rename phy_cable_test_abort to phy_abort_cable_test
      Return different extack when already running test
      Use phy_init_hw() to reset the PHY
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      a68a8138
  2. 07 5月, 2020 2 次提交
    • O
      ethtool: provide UAPI for PHY master/slave configuration. · bdbdac76
      Oleksij Rempel 提交于
      This UAPI is needed for BroadR-Reach 100BASE-T1 devices. Due to lack of
      auto-negotiation support, we needed to be able to configure the
      MASTER-SLAVE role of the port manually or from an application in user
      space.
      
      The same UAPI can be used for 1000BASE-T or MultiGBASE-T devices to
      force MASTER or SLAVE role. See IEEE 802.3-2018:
      22.2.4.3.7 MASTER-SLAVE control register (Register 9)
      22.2.4.3.8 MASTER-SLAVE status register (Register 10)
      40.5.2 MASTER-SLAVE configuration resolution
      45.2.1.185.1 MASTER-SLAVE config value (1.2100.14)
      45.2.7.10 MultiGBASE-T AN control 1 register (Register 7.32)
      
      The MASTER-SLAVE role affects the clock configuration:
      
      -------------------------------------------------------------------------------
      When the  PHY is configured as MASTER, the PMA Transmit function shall
      source TX_TCLK from a local clock source. When configured as SLAVE, the
      PMA Transmit function shall source TX_TCLK from the clock recovered from
      data stream provided by MASTER.
      
      iMX6Q                     KSZ9031                XXX
      ------\                /-----------\        /------------\
            |                |           |        |            |
       MAC  |<----RGMII----->| PHY Slave |<------>| PHY Master |
            |<--- 125 MHz ---+-<------/  |        | \          |
      ------/                \-----------/        \------------/
                                                     ^
                                                      \-TX_TCLK
      
      -------------------------------------------------------------------------------
      
      Since some clock or link related issues are only reproducible in a
      specific MASTER-SLAVE-role, MAC and PHY configuration, it is beneficial
      to provide generic (not 100BASE-T1 specific) interface to the user space
      for configuration flexibility and trouble shooting.
      Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bdbdac76
    • M
      net: phy: add concept of shared storage for PHYs · 63490847
      Michael Walle 提交于
      There are packages which contain multiple PHY devices, eg. a quad PHY
      transceiver. Provide functions to allocate and free shared storage.
      
      Usually, a quad PHY contains global registers, which don't belong to any
      PHY. Provide convenience functions to access these registers.
      Signed-off-by: NMichael Walle <michael@walle.cc>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      63490847
  3. 25 4月, 2020 1 次提交
  4. 23 4月, 2020 1 次提交
  5. 24 3月, 2020 3 次提交
  6. 18 3月, 2020 2 次提交
  7. 15 3月, 2020 1 次提交
  8. 13 3月, 2020 1 次提交
  9. 02 3月, 2020 1 次提交
  10. 25 2月, 2020 1 次提交
    • J
      mdio_bus: Add generic mdio_find_bus() · ce69e216
      Jeremy Linton 提交于
      It appears most ethernet drivers follow one of two main strategies
      for mdio bus/phy management. A monolithic model where the net driver
      itself creates, probes and uses the phy, and one where an external
      mdio/phy driver instantiates the mdio bus/phy and the net driver
      only attaches to a known phy. Usually in this latter model the phys
      are discovered via DT relationships or simply phy name/address
      hardcoding.
      
      This is a shame because modern well behaved mdio buses are self
      describing and can be probed. The mdio layer itself is fully capable
      of this, yet there isn't a clean way for a standalone net driver
      to attach and enumerate the discovered devices. This is because
      outside of of_mdio_find_bus() there isn't a straightforward way
      to acquire the mii_bus pointer.
      
      So, lets add a mdio_find_bus which can return the mii_bus based
      only on its name.
      Signed-off-by: NJeremy Linton <jeremy.linton@arm.com>
      Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ce69e216
  11. 17 2月, 2020 1 次提交
  12. 21 1月, 2020 2 次提交
  13. 20 1月, 2020 1 次提交
  14. 17 1月, 2020 1 次提交
    • F
      net: phy: Maintain MDIO device and bus statistics · 080bb352
      Florian Fainelli 提交于
      We maintain global statistics for an entire MDIO bus, as well as broken
      down, per MDIO bus address statistics. Given that it is possible for
      MDIO devices such as switches to access MDIO bus addresses for which
      there is not a mdio_device instance created (therefore not a a
      corresponding device directory in sysfs either), we also maintain
      per-address statistics under the statistics folder. The layout looks
      like this:
      
      /sys/class/mdio_bus/../statistics/
      	transfers
      	errrors
      	writes
      	reads
      	transfers_<addr>
      	errors_<addr>
      	writes_<addr>
      	reads_<addr>
      
      When a mdio_device instance is registered, a statistics/ folder is
      created with the tranfers, errors, writes and reads attributes which
      point to the appropriate MDIO bus statistics structure.
      
      Statistics are 64-bit unsigned quantities and maintained through the
      u64_stats_sync.h helper functions.
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Tested-by: NAndrew Lunn <andrew@lunn.ch>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      080bb352
  15. 15 1月, 2020 3 次提交
  16. 06 1月, 2020 1 次提交
  17. 26 12月, 2019 2 次提交
  18. 21 12月, 2019 1 次提交
  19. 20 12月, 2019 2 次提交
  20. 26 11月, 2019 1 次提交
  21. 24 11月, 2019 1 次提交
  22. 19 11月, 2019 1 次提交
  23. 24 10月, 2019 1 次提交
  24. 05 10月, 2019 2 次提交
  25. 28 8月, 2019 1 次提交
    • M
      Add genphy_c45_config_aneg() function to phy-c45.c · 94acaeb5
      Marco Hartmann 提交于
      Commit 34786005 ("net: phy: prevent PHYs w/o Clause 22 regs from calling
      genphy_config_aneg") introduced a check that aborts phy_config_aneg()
      if the phy is a C45 phy.
      This causes phy_state_machine() to call phy_error() so that the phy
      ends up in PHY_HALTED state.
      
      Instead of returning -EOPNOTSUPP, call genphy_c45_config_aneg()
      (analogous to the C22 case) so that the state machine can run
      correctly.
      
      genphy_c45_config_aneg() closely resembles mv3310_config_aneg()
      in drivers/net/phy/marvell10g.c, excluding vendor specific
      configurations for 1000BaseT.
      
      Fixes: 22b56e82 ("net: phy: replace genphy_10g_driver with genphy_c45_driver")
      Signed-off-by: NMarco Hartmann <marco.hartmann@nxp.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      94acaeb5
  26. 18 8月, 2019 1 次提交
  27. 14 8月, 2019 2 次提交
  28. 12 8月, 2019 2 次提交