- 20 4月, 2016 4 次提交
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由 Tim Harvey 提交于
Freescale has stated [1] that the LVDS clock source of the IMX6 does not pass the PCI Gen2 clock jitter test, therefore unless an external Gen2 compliant external clock source is present and supplied back to the IMX6 PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance. Add a DT property to specify Gen1 vs Gen2 and check this before allowing a Gen2 link. We default to Gen1 if the property is not present because at this time there are no IMX6 boards in mainline that 'input' a clock on LVDS CLK1/CLK2. In order to be Gen2 compliant on IMX6 you need to: - Have a Gen2 compliant external clock generator and route that clock back to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD reference design). - Specify this clock in the PCIe node in the DT (i.e., IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output). [1] https://community.freescale.com/message/453209Signed-off-by: NTim Harvey <tharvey@gateworks.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Zhu Richard <Richard.Zhu@freescale.com> CC: Akshay Bhat <akshay.bhat@timesys.com> CC: Rob Herring <robh+dt@kernel.org> CC: Shawn Guo <shawnguo@kernel.org>
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由 Petr Štetiar 提交于
Currently the reset-gpio DT property which controls the PCI bus device reset signal defaults to active-low reset sequence (L=reset state, H=operation state) plus the code in reset function isn't GPIO polarity aware - it doesn't matter if the defined reset-gpio is active-low or active-high, it will always result into active-low reset sequence. I've tried to fix it properly and change the reset-gpio reset sequence to be polarity-aware, but this patch has been accepted and then reverted as it has introduced few backward incompatible issues: 1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio polarity correctly: reset-gpio = <&gpio7 12 0>; which means that it's defined as active-high, but in reality it's active-low; thus it wouldn't work without a DTS fix. 2. The logic in the reset function is inverted: gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0) msleep(100); gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1); so even if some of the i.MX6 boards had reset-gpio polarity defined correctly in their DTSes, they would stop working. As we can't break old DTBs, we can't fix them, so we need to introduce this new DT reset-gpio-active-high boolean property so we can support boards with active-high reset sequence. This active-high reset sequence is for example needed on Apalis SoMs, where GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is inverted, active-high. Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana boards (which have active-low PERST#) Signed-off-by: NPetr Štetiar <ynezz@true.cz> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NRob Herring <robh@kernel.org>
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由 Christoph Fritz 提交于
Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch. This patch is heavily based on patches by Richard Zhu. [bhelgaas: factor out refclk enable, fix adjacent typos in imx6q-pcie.txt] Signed-off-by: NChristoph Fritz <chf.fritz@googlemail.com> Acked-by: NRichard Zhu <Richard.Zhu@freescale.com> Acked-by: NLucas Stach <l.stach@pengutronix.de>
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由 Bjorn Helgaas 提交于
Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Tested-by: NChristoph Fritz <chf.fritz@googlemail.com>
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- 06 4月, 2016 1 次提交
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由 Fabio Estevam 提交于
Commit 5c5fb40d ("PCI: imx6: Add support for active-low reset GPIO") cause regressions on some boards like MX6 Gateworks Ventana, for example. The reason for the breakage is that this commit sets the GPIO polarity in the wrong logic level. Also, the commit log is wrong because active-low reset GPIO is what the driver used to support since the beginning. So keep the old behavior that ignores the GPIO polarity specified in the device tree and treat the PCI reset GPIO as active-low. Reported-by: NKrzysztof Hałasa <khalasa@piap.pl> Tested-by: Tim Harvey <tharvey@gateworks.com> # Gateworks Ventana Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NTim Harvey <tharvey@gateworks.com> Acked-by: NLucas Stach <l.stach@pengutronix.de> CC: stable@vger.kernel.org # v4.5+
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- 22 3月, 2016 1 次提交
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由 Sekhar Nori 提交于
Revert 5c3b99d0 ("PCI: dra7xx: Mark driver as broken"). 1c96bee4 ("ARM: DRA7: hwmod: Add custom reset handler for PCIeSS") added support to de-assert PCIe reset, so DRA7x PCIe is not broken anymore. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 21 3月, 2016 1 次提交
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由 Tero Roponen 提交于
Commit e7e127e3 ("PCI: Include pci/hotplug Kconfig directly from pci/Kconfig") added one line to pci/Kconfig. However, for some mysterious reason it isn't there now, even though there are no traces of removing it in the git log. I detected this issue when 'make oldconfig' removed all the options that depended on HOTPLUG_PCI. [bhelgaas: I botched the cfeb8139 ("Merge branch 'pci/host-hv' into next") merge. "git diff cfeb8139^ cfeb8139" shows a conflict in drivers/pci/Kconfig, and I mistakenly dropped the hotplug/Kconfig piece.] Signed-off-by: NTero Roponen <tero.roponen@gmail.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 15 3月, 2016 5 次提交
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由 Heikki Krogerus 提交于
PCI-SIG has defined Interface FEh for Base Class 0Ch, Sub-Class 03h as "USB Device (not host controller)". It is already being used in various USB device controller drivers for matching, so add PCI_CLASS_SERIAL_USB_DEVICE and use it. Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Joao Pinto 提交于
Add a reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP. [bhelgaas: changelog, split patch up, MAINTAINERS update] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Joao Pinto 提交于
Add a default DesignWare "link_up" test for use when a sub-driver doesn't supply its own pcie_host_ops.link_up() method. [bhelgaas: changelog, split into its own patch] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Joao Pinto 提交于
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and spear13xx) had similar loops waiting for the link to come up. Add a generic dw_pcie_wait_for_link() for use by all these drivers so the waiting is done consistently, e.g., always using usleep_range() rather than mdelay() and using similar timeouts and retry counts. Note that this changes the Keystone link training/wait for link strategy, so we initiate link training, then wait longer for the link to come up before re-initiating link training. [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Andreas Ziegler 提交于
Clean up style issues in drivers/pci/pcie/Kconfig, in particular all indentation is now done using tabs, not spaces, and the definition of PCIEASPM_DEBUG is now separated from the definition of PCIEASPM with a newline. Signed-off-by: NAndreas Ziegler <andreas.ziegler@fau.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 12 3月, 2016 15 次提交
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由 Bjorn Helgaas 提交于
Return error immediately to simplify the control flow in pci_create_attr(). No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
If sysfs_create_bin_file() fails, pci_create_attr() leaks the struct bin_attribute it allocated previously. Free the struct bin_attribute if pci_create_attr() fails. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
The value of pdev->rom_attr is the definitive indicator of the fact that we're created a sysfs attribute. Check that rather than rom_size, which is only used incidentally when deciding whether to create a sysfs attribute. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
The IORESOURCE_ROM_COPY and IORESOURCE_ROM_BIOS_COPY bits are unused. Remove them and code that depends on them. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
Remove unnecessary indentation in pci_map_rom(). This is logically part of the previous patch; I split it out to make the critical changes in that patch more obvious. No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
When pci_create_sysfs_dev_files() created the "rom" sysfs file, it set the sysfs file size to the actual size of a ROM BAR, or if there was no ROM BAR but the platform provided a shadow copy in RAM, to 0x20000. 0x20000 is an arch-specific length that should not be baked into the PCI core. Every place that sets IORESOURCE_ROM_SHADOW also sets the size of the PCI_ROM_RESOURCE, so use the resource length always. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 David Daney 提交于
The cavium,pci-thunder-ecam devices are exactly ECAM-based PCI root complexes. These root complexes (loosely referred to as ECAM units in the hardware manuals) are used to access the Thunder on-chip devices. They are special in that all the BARs on devices behind these root complexes are at fixed addresses. Add a driver for these devices that synthesizes Enhanced Allocation (EA) capability entries for each BAR. Since this EA synthesis is needed for exactly two chip models, we can hard- code some assumptions about the device topology and the layout of the config space of specific DEVFNs in the driver. [bhelgaas: changelog, whitespace] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRob Herring <robh@kernel.org>
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由 David Daney 提交于
The root complexes used to access off-chip PCIe devices (called PEM units in the hardware manuals) on some Cavium ThunderX processors require quirky access methods for the config space of the PCIe bridge. Add a driver to provide these config space accessor functions. Use the pci-host-common code to configure the PCI machinery. Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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由 David Daney 提交于
Move pci_host_common_probe() and associated functions to pci-host-common.c, where it can be shared with other drivers. Make it public (not static) and update Kconfig and Makefile to build it. No functional change intended. [bhelgaas: split into separate patch, changelog] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NWill Deacon <will.deacon@arm.com>
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由 David Daney 提交于
Factor gen_pci_probe(), moving most of it into pci_host_common_probe() where it can be shared with other drivers that have slightly different config accessors. No functional change intended. [bhelgaas: split into separate patch, changelog] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NWill Deacon <will.deacon@arm.com>
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由 David Daney 提交于
Move definitions for generic PCI host controller driver structures to a separate header file so we can share them with other drivers. No functional change intended. [bhelgaas: split into separate patch, changelog] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NWill Deacon <will.deacon@arm.com>
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由 Bharat Kumar Gogada 提交于
Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP. [bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix] Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NRavi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NRob Herring <robh@kernel.org>
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由 Shawn Lin 提交于
A SerDes PHY is optional, so if devm_phy_get() doesn't find one at all, that's fine. But if devm_phy_get() finds a PHY that doesn't have a driver yet, it returns -EPROBE_DEFER. In that case, defer probing the Keystone driver. We may be able to load it later after a PHY driver is loaded. [bhelgaas: changelog, check for -EPROBE_DEFER first] Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Ley Foon Tan 提交于
Originally altera_pcie_link_is_up() decided the link was up if any of the low four bits of the LTSSM register were set. But the link is only up if the LTSSM state is L0, so check for that exact value. [bhelgaas: changelog] Signed-off-by: NLey Foon Tan <lftan@altera.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Simon Horman 提交于
Make the R-Car drivers depend on ARCH_RENESAS instead of ARCH_SHMOBILE. This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS. The motivation is that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM-based SoCs. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 11 3月, 2016 4 次提交
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由 Alex Williamson 提交于
Some devices take longer than the spec indicates to return from FLR reset, a notable case of this is Intel integrated graphics (IGD), which can often take an additional 300ms powering down an attached LCD panel as part of the FLR. Allow devices up to 1000ms, testing every 100ms whether the second dword of config space is read as -1. Signed-off-by: NAlex Williamson <alex.williamson@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Joao Pinto 提交于
Add PCI support to ARC and update drivers/pci Makefile enabling the ARC arch to use the generic PCI setup functions. [bhelgaas: fold in Joao's pci-dma-compat.h & pci-bridge.h build fix (I should have caught this myself, sorry] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NVineet Gupta <vgupta@synopsys.com>
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由 Babu Moger 提交于
On some devices, reading or writing VPD causes a system panic. This can be easily reproduced by running "lspci -vvv" or "cat /sys/bus/devices/XX../vpd". Blacklist these devices so we don't access VPD data at all. [bhelgaas: changelog, comment, drop pci/access.c changes] Link: https://bugzilla.kernel.org/show_bug.cgi?id=110681Tested-by: NShane Seymour <shane.seymour@hpe.com> Tested-by: NBabu Moger <babu.moger@oracle.com> Signed-off-by: NBabu Moger <babu.moger@oracle.com> Signed-off-by: NHannes Reinecke <hare@suse.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Alexander Duyck <alexander.duyck@gmail.com>
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由 Bjorn Helgaas 提交于
Use usleep_range() instead of udelay() while waiting for a VPD access to complete. This is not a performance path, so no need to hog the CPU. Rationale for usleep_range() parameters: We clear PCI_VPD_ADDR_F for a read (or set it for a write), then wait for the device to change it. For a device that updates PCI_VPD_ADDR between our config write and subsequent config read, we won't sleep at all and can get the device's maximum rate. Sleeping a minimum of 10 usec per 4-byte access limits throughput to about 400Kbytes/second. VPD is small (32K bytes at most), and most devices use only a fraction of that. We back off exponentially up to 1024 usec per iteration. If we reach 1024, we've already waited up to 1008 usec (16 + 32 + ... + 512), so if we miss an update and wait an extra 1024 usec, we can still get about 1/2 of the device's maximum rate. Tested-by: NShane Seymour <shane.seymour@hpe.com> Tested-by: NBabu Moger <babu.moger@oracle.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NHannes Reinecke <hare@suse.com>
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- 09 3月, 2016 9 次提交
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由 Wei Yang 提交于
This adds weak function pcibios_bus_add_device() for arch dependent code could do proper setup. For example, powerpc could setup EEH related resources for SRIOV VFs. Signed-off-by: NWei Yang <weiyang@linux.vnet.ibm.com> Reviewed-by: NGavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
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由 Wei Yang 提交于
During EEH recovery, hotplug is applied to the devices which don't have drivers or their drivers don't support EEH. However, the hotplug, which was implemented based on PCI bus, can't be applied to VF directly. Instead, we unplug and plug individual PCI devices (VFs). This renames virtn_{add,remove}() and exports them so they can be used in PCI hotplug during EEH recovery. Signed-off-by: NWei Yang <weiyang@linux.vnet.ibm.com> Reviewed-by: NGavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
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由 Jean Delvare 提交于
Log successful error injections so that injected errors can be differentiated from real errors. Suggested-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Borislav Petkov <bp@suse.de>
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由 Jean Delvare 提交于
The aer_inject driver is very quiet. In most cases, it merely returns an error code to user-space, leaving the user with little clue about the actual reason for the failure. So, log error messages for 4 of the most frequent causes of failure: * Can't find the root port of the specified device. * Device doesn't support AER. * Root port doesn't support AER. * AER device not found. This gives the user a chance to understand why aer-inject failed. Based on a preliminary patch by Thomas Renninger. Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Borislav Petkov <bp@suse.de> CC: Thomas Renninger <trenn@suse.de>
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由 Jean Delvare 提交于
dev_warn() is better than printk(LOG_WARNING...) as it records which device the message relates to. Also add a prefix "aer_inject:" to help differentiate real errors from injected errors. Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Borislav Petkov <bp@suse.de>
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由 Jean Delvare 提交于
EPERM means "Operation not permitted", which doesn't reflect the lack of support for AER. EPROTONOSUPPORT (Protocol not supported) is a better choice of error code if the device or its root port lack support for AER. Likewise, EINVAL means "Invalid argument", which is not suitable for cases where the AER error device is missing or unusable. ENODEV and EPROTONOSUPPORT, respectively, fit better. Suggested-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NJean Delvare <jdelvare@suse.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Borislav Petkov <bp@suse.de> CC: Prarit Bhargava <prarit@redhat.com>
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由 Thierry Reding 提交于
BARs are disabled when the size register is 0, so it's misleading to write a base address into the start register. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Thierry Reding 提交于
Track the offsets of the bus -> CPU mapping for I/O and memory. This is cosmetic for current Tegra chips because the offset is always 0. But to properly support legacy use-cases, like VGA, this would be needed so that PCI bus addresses can be relocated. While at it, also request the I/O resource both in physical memory and I/O space to make /proc/iomem consistent, as well as add the I/O region to the list of host bridge resources. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Thierry Reding 提交于
The num_ports field of the tegra_pcie structure is never used so remove it. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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