Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Header Changes]
  - Add command for retrieving PSR residency
  - Add command for forcing PSR static
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Fail and restart timing for HDCP1 retry occurs too quickly.
This would cause some MST monitors to show black screen.

[How]
Adjusted timing of fail and restart to 200ms.
Signed-off-by: NJake Wang <haonan.wang2@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Commit "Blank HUBP during pixel data blank for DCN30 v2"
modifies HW behaviour during blank, which might have OS
dependencies. We need to assess the impact on amdgpu_dm
and only re-enable HUBP blanking when all necessary
changes are understood.

[How]
 - revert functional changes
 - leave architectural changes intact
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Customer make a request to add this WA by driver.

Some MUX chips will power down with eDP 1.4 panel and
lose previous supported link rates(DPCD 0x010) in
customer's hybrid-GPU designs. As a result, during sleep
resuming and screen turns on from idle, link training
will be performed incorrectly and eDP will flicker or
black screen. These MUX chips need source to read DPCD
0x010 again during LKT so that it can restore supported
link rates of panel.

For driver side, supported link rate set is fetched when
link detection, no need to update but just read again
as WA.

[How]
Read DPCD 0x010 again during link training for eDP 1.4.
Signed-off-by: NDale Zhao <dale.zhao@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Currently, we only support calculating CRC on whole frame.
We want to extend the capability to calculate CRC on
specific frame area.

[how]
Calculate CRC on specific area once it's specified from the
input parameter.
Signed-off-by: NWayne Lin <Wayne.Lin@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
There is a DRM_ERROR when the dc_sink is NULL and
there should not be this warning when the connector
is forced.

[how]
Do not warn if dc_sink is NULL if the connector
is forced.
Signed-off-by: NVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Prior commit "Blank HUBP during pixel data blank for DCN30"
missed the call to set_disp_pattern_generator from
set_crtc_test_pattern, which re-exposed the issue for which
we initially blocked active-only p-state switching.

[How]
 - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version
 - new hwss funciton set_disp_pattern_generator
 - dcn20 version just calls opp_set_disp_pattern_generator
 - dcn30 version implements the HUBP blank
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When checking if we want to disable GSL or not,
we should reset flip_immediate to be the flip type
of the topmost plane before looping through the
other planes.

[How]
Set flip_immediate to be the flip type of the topmost
plane before looping through the other planes.
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We want to trigger atomic check on connector when
DSC debugfs properties are changed. The previous
method was reverted because it accessed connector
properties unsafely and would also heavily
impact performance.

[How]
Add a flag for forcing DSC update in CRTC state
and add connector to the state if the flag is set.
Signed-off-by: NEryk Brol <eryk.brol@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.

[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.
Signed-off-by: NHugo Hu <hugo.hu@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The OPTC memory blocks should be powered down when they are not in use.
This will reduce power consumption.

[How]
1. Set ODM_MEM_UNASSIGNED_PWR_MODE to shutdown memory when unassigned
2. Set ODM_MEM_VBLANK_PWR_MODE to light sleep mode when in vblank
3. Added a debug option to allow this behaviour to be turned off
4. Restructured debug options to use a bitfield in a way that's more clear
Signed-off-by: NJacky Liao <ziyu.liao@amd.com>
Reviewed-by: NEric Yang <eric.yang2@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.

[How]
Implement same register space to future
resource files.
Signed-off-by: NChris Park <Chris.Park@amd.com>
Reviewed-by: NJoshua Aberback <Joshua.Aberback@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
If pbn_per_slot is 0, fail instead of dividing by zero and
bugchecking.

[how]
Check for zero divisor before division operation.
Signed-off-by: NAshley Thomas <Ashley.Thomas2@amd.com>
Reviewed-by: NWyatt Wood <Wyatt.Wood@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
There are some timings for which we support p-state
switching in active, but not in blank. There was a
previous issue where a timing that had active-only
support would hang a p-state request when we were in
an extended blanking period. The workaround for that
issue was to block active-only p-state switching,
but that resulted in a lack of p-state support for
some common timings such as 1440p60. We want to fix
that issue properly by un-blocking p-state requests
while the display is blanked, so that we can re-enable
active-only p-state switching.

[How]
 - new version of blank_pixel_data for DCN30
 - call hubp->set_blank from dcn30_blank_pixel_data
 - blank every hubp in the mpcc tree, and odm tree
 - on blank enable, wait until the next frame before blanking HUBP
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Driver keeps the invalid information cause report the
incorrect monitor which save in remote sink to OS

[How]
When connector type change from MST to non-MST,
stop the topology manager.
Signed-off-by: NLewis Huang <Lewis.Huang@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When enabling PIP in Heaven, the PIP planes are VSYNC
flip and is also the top-most pipe. In this case GSL
will be disabled because we only check immediate flip
for the top pipe. However, the desktop planes are still
flip immediate so we should at least keep GSL on until
the full update.

[How]
Check each pipe in the tree to see if any planes
are flip immediate. Maintain the GSL lock if yes,
and take it down after when unlocking if any planes
are flipping VSYNC. Keeping GSL on with VSYNC +
flip immediate planes causes corruption.
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.

[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max prefetch mode to 0 by default.
Signed-off-by: NIsabel Zhang <isabel.zhang@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
1. only need to check first ODM pipe.
2. Only need to check eDP which is on.
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The MPC memory blocks in DCN3 should be powered down completely when
they are not in use. This will reduce power consumption.

[How]
This commits changes behaviour for dcn3 and does the following:
1. Write to MPC_RMU<X>_LOW_PWR_MODE and MPCC_OGAM_MEM_LOW_PWR_MODE to
   automatically shut down memory when not in use
2. mpc3_power_on_shaper_3dlut and mpc3_power_on_ogam_lut are called
   to disable force power on when configuration finishes
3. Added a debug option to allow this behaviour to be turned off
Signed-off-by: NJacky Liao <ziyu.liao@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The C standard does not specify whether an enum is signed or unsigned.
In the function prototype, one of the argument is defined as an enum
but its declaration was unit32_t. Fix this by changing the function
argument to enum in the declaration.
Signed-off-by: NTao.Huang <Tao.Huang@amd.com>
Signed-off-by: NFlorin Iucha <florin.iucha@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

gcc -Wextra warns about a function taking an enum argument
being called with a bool:

drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c: In function 'apply_degamma_for_user_regamma':
drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:1617:29: warning: implicit conversion from 'enum <anonymous>' to 'enum dc_transfer_func_predefined' [-Wenum-conversion]
 1617 |  build_coefficients(&coeff, true);

It appears that a patch was added using the old calling conventions
after the type was changed, and the value should actually be 0
(TRANSFER_FUNCTION_SRGB) here instead of 1 (true).

Fixes: 55a01d40 ("drm/amd/display: Add user_regamma to color module")
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Concurrent operation of VCN and JPEG decoder in DPG mode is
causing ring timeout due to power state.
Signed-off-by: NVeerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: NLeo Liu <leo.liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We're unconditionally using modifiers internally for GFX9+ now.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This expose modifier support on GFX9+.

Only modifiers that can be rendered on the current GPU are
added. This is to reduce the number of modifiers exposed.

The HW could expose more, but the best mechanism to decide
what to expose without an explosion in modifiers is still
to be decided, and in the meantime this should not regress
things from pre-modifiers and does not risk regressions as
we make up our mind in the future.

v2:
  - Added comment that D on Raven is only valid for 64bpp
    and will be filtered based on format later.
  - Removed D tiling modes that weren't useful for 64bpp
    on GFX10+.

v4: Add AMDGPU_FAMILY_VGH case.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For DCC we will use 2/3 planes to avoid X rendering to the frontbuffer
with DCC compressed images. To make this work with the core KMS
validation we need to add extra formats with the extra planes.

However, due to flexibility we set bpp = 0 for the extra planes and
do the validation ourselves.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This sets the DC tiling options from the modifier, if modifiers
are used for the FB. This patch by itself does not expose the
support yet though.

There is not much validation yet to limit the scope of this
patch, but the current validation is at the same level as
the BO metadata path.

v2: Add modifier check to should_reset_plane.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Prepare for inserting modifiers based configuration, while sharing
a bunch of DCC validation & initializing the device-based configuration.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This way the modifier path gets exercised all the time, improving
testing. Furthermore, for modifiers this is required as getfb2
will always return the modifier if the driver sets allow_fb_modifiers.

This only triggers once allow_fb_modifiers is set.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This moves the tiling_flags to the framebuffer creation.
This way the time of the "tiling" decision is the same as it
would be with modifiers.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds modifiers for GFX9+ AMD GPUs.

As the modifiers need a lot of parameters I split things out in
getters and setters.
  - Advantage: simplifies the code a lot
  - Disadvantage: Makes it harder to check that you're setting all
                  the required fields.

The tiling modes seem to change every generation, but the structure
of what each tiling mode is good for stays really similar. As such
the core of the modifier is
 - the tiling mode
 - a version. Not explicitly a GPU generation, but splitting out
   a new set of tiling equations.

Sometimes one or two tiling modes stay the same and for those we
specify a canonical version.

Then we have a bunch of parameters on how the compression works.
Different HW units have different requirements for these and we
actually have some conflicts here.

e.g. the render backends need a specific alignment but the display
unit only works with unaligned compression surfaces. To work around
that we have a DCC_RETILE option where both an aligned and unaligned
compression surface are allocated and a writer has to sync the
aligned surface to the unaligned surface on handoff.

Finally there are some GPU parameters that participate in the tiling
equations. These are constant for each GPU on the rendering/texturing
side. The display unit is very flexible however and supports all
of them :|

Some estimates:
 - Single GPU, render+texture: ~10 modifiers
 - All possible configs in a gen, display: ~1000 modifiers
 - Configs of actually existing GPUs in a gen: ~100 modifiers

For formats with a single plane everything gets put in a separate
DRM plane. However, this doesn't fit for some YUV formats, so if
the format has >1 plane, we let the driver pack the surfaces into
1 DRM plane per format plane.

This way we avoid X11 rendering onto the frontbuffer with DCC, but
still fit into 4 DRM planes.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

With modifiers I'd like to support non-dedicated buffers for
images.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: stable@vger.kernel.org # 5.1.0
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Otherwise the field ends up being used uninitialized when
enabling modifiers, failing validation with high likelyhood.

v4: Use memset
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
(for v1)
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Silently accepting it could result in corruption.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix the compile warnings below:
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13: warning: variable 'min' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13: warning: variable 'max' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reported-by: Nkernel test robot <lkp@intel.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix the warning below:
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:29: warning: no previous prototype for function 'asic_internal_ss_get_ss_table' [-Wmissing-prototypes]
   ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
                               ^
   drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
   ^
   static
   1 warning generated.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reported-by: Nkernel test robot <lkp@intel.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Correct spelling in one of the comment.

s/defalut/default/p
Signed-off-by: NBhaskar Chowdhury <unixbhaskar@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>