Since the driver was written an is_prepared() operation has been made
possible. Since the driver uses I2C I/O only prepare operations are
provided so move the is_enabled() operation over to is_prepared().
Signed-off-by: NMark Brown <broonie@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

parent of hdmi and mixer block is mentioned as aclk200 which is
not correct. It is clocked by the ouput of aclk200_disp1. Hence
parent for mixer and hdmi clocks is changed to aclk200_disp1.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Cc: Emilio López <emilio@elopez.com.ar>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: refreshed patch based on sunxi changes]

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NGregory Clement <gregory.clement@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NGregory Clement <gregory.clement@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NGregory Clement <gregory.clement@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NGregory Clement <gregory.clement@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

While at it also make 'u300_clk_lookup' static as it is used only
in this file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Allwinner clock changes for 3.12

These patches mostly do some cleanup to introduce the basic gated clocks for
the Allwinner A10s, A20 and A31 SoCs.

Conflicts:
	drivers/clk/sunxi/clk-sunxi.c

the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals

wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: NGerhard Sittig <gsi@denx.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Currently of_clk_init() finds a matching device node while holding
the device tree spinlock.  When a matching device node is found, the
lock is dropped and then re-acquired in order to get a reference
to the matching device id structure.

Acquiring the spinlock twice is unnecessary (and it opens a
vulnerable window that could conceivably lead to errors).

There already exists an interface for both finding and taking a
reference to a device id under lock, so use it.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NChristian Daudt <csd@broadcom.com>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <matt.porter@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

With the recent move towards CLK_OF_DECLARE(...), the driver stopped
initializing osc32k, which is compatible "fixed-clock". This is because
we never called of_clk_init(NULL). Fix this by moving the only other
simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL)
to initialize both of them.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch modifies PLL6552 and PLL6553 clock drivers to use recently
added common Samsung PLL registration method.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The Allwinner A20 is almost identical to the earlier A10 SoC from
Allwinner on many aspects, including the clocks tree. However, since the
A20 has some additionnal IPs compared to the A10, the clock tree isn't
exactly the same, especially when it comes to the gated clocks
available. We thus need to register different clock gates for the A20.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NEmilio López <emilio@elopez.com.ar>

The A31 has a mostly different clock set compared to the other older
SoCs currently supported in the Allwinner clock driver.

Add support for the basic useful clocks. The other ones will come in
eventually.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NEmilio López <emilio@elopez.com.ar>

The divider width used to be hardcoded. Some A31 dividers are no longer
with the hardcoded width, so we need to make it specific to each divider
and set it in the dividers data.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NEmilio López <emilio@elopez.com.ar>

Rename all the generic-named structure to sun4i to avoid confusion when
we will introduce the sun6i (A31) clocks.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NEmilio López <emilio@elopez.com.ar>

With the recent move towards CLK_OF_DECLARE(...), the driver stopped
initializing osc32k, which is compatible "fixed-clock". This is because
we never called of_clk_init(NULL). Fix this by moving the only other
simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL)
to initialize both of them.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>

The Allwinner A10s has a slightly different gates set than the A10 and
A13, so add these gates to the clk driver.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: NEmilio López <emilio@elopez.com.ar>
Reviewed-by: NEmilio López <emilio@elopez.com.ar>

Add missing iounmap to setup error path.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

At some point changes to clk_set_rate and clk_set_parent introduced a
bug whereby NULL struct clk pointers were treated as an error. This is
in violation of the API in include/linux/clk.h. Reintroduce graceful
handling of NULL clk's by bailing from clk_set_rate and clk_set_parent
with return codes of zero.
Signed-off-by: NMike Turquette <mturquette@linaro.org>

arm: Xilinx Zynq clock changes for v3.12

Just small two changes where the first fixes
documentation and the second improves
code readability.

Use more descriptive #defines for the minimum and maximum PLL
feedback divider.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't
set. This implements determine_rate for clk-mux to propagate to each
parent and to choose the best one (like clk-divider this chooses the
parent which provides the fastest rate <= the requested rate).

The determine_rate op is implemented as a core helper function so that
it can be easily used by more complex clocks which incorporate muxes.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add core support to allow clock implementations to select the best
parent clock when rounding a rate, e.g. the one which can provide the
closest clock rate to that requested. This is by way of adding a new
clock op, determine_rate(), which is like round_rate() but has an extra
parameter to allow the clock implementation to optionally select a
different parent clock. The core then takes care of reparenting the
clock when setting the rate.

The parent change takes place with the help of some new private data
members. struct clk::new_parent specifies a clock's new parent (NULL
indicates no change), and struct clk::new_child specifies a clock's new
child (whose new_parent member points back to it). The purpose of these
are to allow correct walking of the future tree for notifications prior
to actually reparenting any clocks, specifically to skip child clocks
who are being reparented to another clock (they will be notified via the
new parent), and to include any new child clock. These pointers are set
by clk_calc_subtree(), and the new_child pointer gets cleared when a
child is actually reparented to avoid duplicate POST_RATE_CHANGE
notifications.

Each place where round_rate() is called, determine_rate() is checked
first and called in preference. This restructures a few of the call
sites to simplify the logic into if/else blocks.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Move some parent related functions up in clk.c so they can be used by
the modifications in the following patch which enables clock reparenting
during set_rate. No other changes are made so this patch makes no
functional difference in isolation. This is separate from the following
patch primarily to ease readability of that patch.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Abstract access to the clock parent cache by defining
clk_get_parent_by_index(clk, index). This allows access to parent
clocks from clock drivers.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NMike Turquette <mturquette@linaro.org>

These registration calls may be used by loadable modules. Export them.
Signed-off-by: NMike Turquette <mturquette@linaro.org>

clk_register_divider() needs to be exported so that it could be used
in a module driver, otherwise we get the following error:

ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined!
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: also export clk_register_divider_table]

Export this symbol so that modules can register fixed rate
clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>