Correct misspelling, "emda3" -> "edma3".
Reported-by: NAdam J Allison <adamj.allison@gmail.com>
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Rename the tag of the 3.3 V regulator used in the DRA72 EVM in
order to have a consistent tag name with the DRA7 EVM.  This
is useful when the regulator needs to be referenced in common
dtsi files (i.e. for common companion boards like JAMR3 [1]).

[1] http://www.ti.com.cn/cn/lit/ug/sprui52/sprui52.pdfSigned-off-by: NMisael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

AM335x ICE board has a TI PCA9536 chip connected to I2C0 at address
0x41. Add DT entry for the same.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NKristofer Martinez <Kristofer.S.Martinez@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add an operating-points-v2 table with all OPPs available for all silicon
revisions along with necessary data for use by ti-opp driver to selectively
enable the appropriate OPPs at runtime and handle voltage transitions

As we now need to define voltage ranges for each OPP, we define the
minimum and maximum voltage to match the ranges possible for AVS class0
voltage as defined by the DRA7/AM57 Data Manual, with the exception of
using a range for OPP_OD based on historical data to ensure that SoCs
from older lots still continue to boot, even though more optimal voltages
are now the standard. Once an AVS Class0 driver is in place it will be
possible for these OPP voltages to be adjusted to any voltage within the
provided range.

Information from SPRS953, Revised December 2015.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Nearly all of the information in the cpus node, especially for cpu0, is
the same between dra74x and dra72x so move the common information to
the parent dra7.dtsi to avoid duplication of data.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Create a system control module node for the control module portion that
resides under l4_wkup.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Hook dcdc2 as the cpu0-supply.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add an operating-points-v2 table with all OPPs available for all silicon
revisions along with necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime.

Information from AM437x Data Manual, SPRS851B, Revised April 2015,
Table 5-2.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Although all PG2.0 silicon may not support 1GHz OPP for the MPU, older
Beaglebone Blacks may have PG2.0 silicon populated and these particular
parts are guaranteed to support the OPP, so enable it for PG2.0 on
am335x-boneblack only.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Drop the operating-points table present in am33xx.dtsi and add an
operating-points-v2 table with all OPPs available for all silicon
revisions along with necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime. Also, drop the voltage-tolerance
value and provide voltages for each OPP using the <target min max>
format instead.

Information from AM335x Data Manual, SPRS717i, Revised December 2015,
Table 5-7.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Now that we are moving to OPPv2 bindings and able to add 1GHz OPP for
MPU, let's update the max MPU voltage range to align with the maximum
possible value allowed in the operating-points table, which is max
target voltage of 132500 uV + 2%.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Without that change wifi card isn't probed because pwrseq is necessary for
libertas chip.
Signed-off-by: NH. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Define pinmux and usage if irq pin.
Signed-off-by: NH. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Define pinmux and usage if irq pin + fix irq edge.
Signed-off-by: NH. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add pinmux and usage of bma180 irq pin.
Signed-off-by: NH. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Define pwm backlight node which is using dmtimer pwm.
Signed-off-by: NMarek Belisko <marek@goldelico.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add the needed DT data to enable IR TX driver
Signed-off-by: NIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Secure variants of DRA7xx and AM57xx SoCs may need to reserve a region
of the SRAM for use by secure software. To account for this, add a child
node to the ocmcram1 node that will act as a placeholder at the start
of the SRAM for the reserved region of memory that may be required
by secure services. The node is added with size 0 so that by default
parts will have the full space available but the bootloader or board dts
file is able to resize the node as needed depending on how much reserved
space is needed, if any, so end users of the ocmcram1 region on HS parts
must be aware that a smaller amount of SRAM than expected may be available.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Reviewed-by: NAndreas Dannenberg <dannenberg@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add all ocmcram nodes to dra7.dtsi using the generic mmio-sram driver.
DRA7xx and AM57xx families of SoCs can contain three ocmcram regions of
SRAM, one of 512kb and also an optional two additional of 1Mb each. Mark
the two additional 1MB regions of SRAM as disabled as only ocmcmram1 is
on all variants of the SoCs, then depending on which specific variant
is in use the ocmcram2 and ocmcram3 nodes can be enabled in the board
dts file if the data manual for that part number indicates the ocmcram
region is available.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Reviewed-by: NAndreas Dannenberg <dannenberg@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: NVignesh R <vigneshr@ti.com>
[fcooper@ti.com: Add eCAP and use updated bindings for PWMSS and ePWM]
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Previous patches switched the ECAP and EPWM to use the new bindings.
These bindings explicitly adds the various required clocks via DT rather
than depending on hwmod.

Therefore, it is safe to remove the hwmod entries since they are no longer
needed.
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Switch to a new ECAP and EPWM bindings that doesn't depend on hwmod to
provide the various required clocks.

For AM437 and AM335x, add the required clocks explicitly to DT. The
hwmod entries for ECAP and EPWM will be removed and this will prevent
anything from breaking.
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The memory range assigned to the PMC (Power Management Controller) was
not including the PMC_PCR register which are used to control peripheral
clocks.

This was working fine thanks to the page granularity of ioremap(), but
started to fail when we switched to syscon/regmap, because regmap is
making sure that all accesses are falling into the reserved range.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: NRichard Genoud <richard.genoud@gmail.com>
Tested-by: NRichard Genoud <richard.genoud@gmail.com>
Fixes: 863a81c3 ("clk: at91: make use of syscon to share PMC registers in several drivers")
Cc: <stable@vger.kernel.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The device driver was added in v4.5 by commit dca536c4
("watchdog: add support for Sigma Designs SMP86xx/SMP87xx")
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This platform will use the new generic platdev driver.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Commit fefe0535 ("clk: tango4: improve clkgen driver") added
support for USB and SDIO clocks.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Define the CPU temperature sensor, and critical trip point.

Commit 799d71da471c ("add temperature sensor support for tango SoC")
added the device driver.
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

An error in documentation of the NAND Flash Controller (NFC) led to choose
another compatibility string for sama5d2 with an impact on the NAND flash
ready/busy information. It was producing the error message:

atmel_nand 80000000.nand: Time out to wait for interrupt: 0x08000000

and had an impact on performance.

So, switch back to the classical "atmel,sama5d3-nfc" compatibility string for
this SoC which gives the proper ready/busy bit information. The NAND flash
driver will be updated to remove the support for this different
implementation.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NRomain Izard <romain.izard.pro@gmail.com>
[nicolas.ferre@atmel.com: change commit message]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This adds a common device tree for all fifth generation Aspeed systems,
and a board specific device tree for the ast2500 evaluation board.
Signed-off-by: NJoel Stanley <joel@jms.id.au>

A common device tree for all forth gen/ast2400 systems and a board
specific dts for the Palmetto OpenPower developemnt machine which was
used for testing.
Signed-off-by: NJoel Stanley <joel@jms.id.au>

Enable pll3 and pll7 clocks that are needed by display clocks.
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

There are 3 kinds of OLinuXino Lime2 boards.
One without any on board storage, one with NAND storage and one with
eMMC storage. This patch adds the eMMC variant of boards.

eMMC storage is different from a regular SD card in that it is soldered
on the board and cannot be changed. Additionally, it shares pins with
the NAND module and with the second SPI port.
Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl>
[Maxime: Removed the change log from the commit log]
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

MAX8997 PMIC requires interrupt and fails probing without it.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Fixes: d105f0b1 ("ARM: dts: Add basic dts file for Samsung Trats board")
Cc: <stable@vger.kernel.org>
[k.kozlowski: Write commit message, add CC-stable]
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

The usage of slash character causes failure when creating regulator
debugfs entry.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
[k.kozlowski: Write commit message]
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

The MFC nodes with the memory regions reserved for memory allocations
are missing in the Exynos5420 Peach Pit and Exynos5800 Peach Pi DTS.

This causes the s5p-mfc driver probe to fail with the following error:

[    4.140647] s5p_mfc_alloc_memdevs:1072: Failed to declare coherent memory for MFC device
[    4.216163] s5p-mfc: probe of 11000000.codec failed with error -12

Add the missing nodes so the driver probes and the {en,de}coder video
nodes are registered correctly:

[    4.096277] s5p-mfc 11000000.codec: decoder registered as /dev/video4
[    4.102282] s5p-mfc 11000000.codec: encoder registered as /dev/video5
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Add node to support SAMA5D4 hardware random number generator.
Signed-off-by: NMike Williams <mike@mikebwilliams.com>
[nicolas.ferre@atmel.com: reduce the register map size]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add node to support SAMA5D3 hardware random number generator.
Signed-off-by: NMike Williams <mike@mikebwilliams.com>
[nicolas.ferre@atmel.com: reduce the register map size]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add node to support SAMA5D2 hardware random number generator.
Signed-off-by: NMike Williams <mike@mikebwilliams.com>
[nicolas.ferre@atmel.com: reduce the register map size]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

No need to map 0x4000 bytes for the TRNG device: reduce it to 0x100.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Enable pll3 and pll7 clocks that are needed to drive display clocks.
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>