snps databook noted that physical coding sublayer (PCS) interface
that can be used when the MAC is configured for the TBI, RTBI, or
SGMII PHY interface. we have RGMII and SGMII in a SoC and it also
has the PCS block. it needs stmmac_init_phy and stmmac_mdio_register
function for initializing phy when it used RGMII interface.
Signed-off-by: NDejin Zheng <zhengdejin5@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When HW does not support perfect filtering the feature will not be
enabled in the net_device. Add a check for this to prevent failures.

Fixes: 1b2250a0 ("net: stmmac: selftests: Add tests for VLAN Perfect Filtering")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When the VLAN ID does not match the expected one it means filter failed
in HW. Fix it.

Fixes: 94e18382 ("net: stmmac: selftests: Add selftest for VLAN TX Offload")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Synopsys AXS101 boards do not support unaligned memory loads or stores.
Change the selftests mechanism to explicity:
- Not add extra alignment in TX SKB
- Use the unaligned version of ether_addr_equal()

Fixes: 091810db ("net: stmmac: Introduce selftests support")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add a new test for TBS feature which is used in ETF scheduler. In this
test, we send a packet with a launch time specified as now + 500ms and
check if the packet was transmitted on that time frame.

Changes from v2:
- Use the TBS bitfield
- Remove debug message
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

In the upcoming commit for TBS selftest we will need to send a packet on
a specific Queue. As stmmac fallsback to netdev_pick_tx() on the select
Queue callback, we need to switch all selftests logic to
dev_direct_xmit() so that we can send the given SKB on a specific Queue.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

Adds more information regarding HW Capabilities in the corresponding
DebugFS file.

Changes from v2:
- Remove the TX/RX queues in use (Jakub)
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

Enable TBS support on GMAC5 PCI entry for all Queues except Queue 0.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

Adds all the necessary HW hooks to support TBS feature in QoS cores.

Changes from v1:
- Remove unneeded LT shift as the IP already does this.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

Adds all the necessary HW hooks to support TBS feature in XGMAC cores.

Changes from v1:
- Remove unneeded LT shift as the IP already does this.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

Adds the support for ETF scheduler using TBS feature which is available
in XGMAC and QoS IPs.

Changes from v2:
- Fix checkpatch issues (Jakub)
- Use the TBS bitfield
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

Adds the initial hooks for TBS support. This needs a 32 byte descriptor
in order for it to work with current HW. Adds all the logic for Enhanced
Descriptors in main core but no HW related logic for now.

Changes from v2:
- Use bitfield for TBS status / support (Jakub)
- Remove unneeded cache alignment (Jakub)
- Fix checkpatch issues
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NJakub Kicinski <kuba@kernel.org>

RSS, when enabled, will bypass the L3 and L4 filtering causing it not
to work. Add a check before trying to setup the filters.

Fixes: 425eabdd ("net: stmmac: Implement L3/L4 Filters using TC Flower")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

We are disabling RSS on HW but not updating the internal private status
to the 'disabled' state. This is needed for next tc commit that will
check if RSS is disabled before trying to apply filters.

Fixes: 4647e021 ("net: stmmac: selftests: Add selftest for L3/L4 Filters")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

If FPE is supposed to be disabled we need to return after disabling it.

Fixes: 7c728274 ("net: stmmac: gmac5+: Add support for Frame Preemption")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

If FPE is supposed to be disabled we need to return after disabling it.

Fixes: f0e56c8d ("net: stmmac: xgmac3+: Add support for Frame Preemption")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

All members of mdio_bus_data are cleared to 0 when it was obtained
by devm_kzalloc(). so It doesn't need to set phy_mask as 0 again.
Signed-off-by: NDejin Zheng <zhengdejin5@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Allow all the RGMII modes to be used. This would allow us to represent
the hardware better in the device tree with RGMII_ID where in most
cases the PHY's internal delay for both RX and TX are used.

Fixes: 9f93ac8d ("net-next: stmmac: Add dwmac-sun8i")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Allow all the RGMII modes to be used. This would allow us to represent
the hardware better in the device tree with RGMII_ID where in most
cases the PHY's internal delay for both RX and TX are used.

Fixes: af0bd4e9 ("net: stmmac: sunxi platform extensions for GMAC in Allwinner A20 SoC's")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When using fixed link we don't need the MDIO bus support.
Reported-by: NHeiko Stuebner <heiko@sntech.de>
Reported-by: Nkernelci.org bot <bot@kernelci.org>
Fixes: d3e014ec ("net: stmmac: platform: Fix MDIO init for platforms without PHY")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Acked-by: NSriram Dash <Sriram.dash@samsung.com>
Tested-by: NPatrice Chotard <patrice.chotard@st.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail> # Lamobo R1 (fixed-link + MDIO sub node for roboswitch).
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add one notifier for udev changes net device name.
Fixes: b6601323ef9e ("net: stmmac: debugfs entry name is not be changed when udev rename")
Signed-off-by: NJiping Ma <jiping.ma2@windriver.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

GXBB and newer SoCs use the fixed FCLK_DIV2 (1GHz) clock as input for
the m250_sel clock. Meson8b and Meson8m2 use MPLL2 instead, whose rate
can be adjusted at runtime.

So far we have been running MPLL2 with ~250MHz (and the internal
m250_div with value 1), which worked enough that we could transfer data
with an TX delay of 4ns. Unfortunately there is high packet loss with
an RGMII PHY when transferring data (receiving data works fine though).
Odroid-C1's u-boot is running with a TX delay of only 2ns as well as
the internal m250_div set to 2 - no lost (TX) packets can be observed
with that setting in u-boot.

Manual testing has shown that the TX packet loss goes away when using
the following settings in Linux (the vendor kernel uses the same
settings):
- MPLL2 clock set to ~500MHz
- m250_div set to 2
- TX delay set to 2ns on the MAC side

Update the m250_div divider settings to only accept dividers greater or
equal 2 to fix the TX delay generated by the MAC.

iperf3 results before the change:
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.00  sec   182 MBytes   153 Mbits/sec  514      sender
[  5]   0.00-10.00  sec   182 MBytes   152 Mbits/sec           receiver

iperf3 results after the change (including an updated TX delay of 2ns):
[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
[  5]   0.00-10.00  sec   927 MBytes   778 Mbits/sec    0      sender
[  5]   0.00-10.01  sec   927 MBytes   777 Mbits/sec           receiver

Fixes: 4f6a71b8 ("net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration")
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The current implementation of "stmmac_dt_phy" function initializes
the MDIO platform bus data, even in the absence of PHY. This fix
will skip MDIO initialization if there is no PHY present.

Fixes: 74371272 ("net: stmmac: Convert to phylink and remove phylib logic")
Acked-by: NJayati Sahu <jayati.sahu@samsung.com>
Signed-off-by: NSriram Dash <sriram.dash@samsung.com>
Signed-off-by: NPadmanabhan Rajanbabu <p.rajanbabu@samsung.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

For ARCHs that don't support 64 bits division we need to use the
helpers.

Fixes: b60189e0 ("net: stmmac: Integrate EST with TAPRIO scheduler API")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This can be useful for debug. Add these counters on GMAC5+ cores just
like we did for XGMAC.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Adds the HW specific support for Frame Preemption on XGMAC3+ cores.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Adds the HW specific support for Frame Preemption on GMAC5+ cores.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Adds the support for Frame Preemption using TAPRIO API. This works along
with EST feature and allows to select if preemptable traffic shall be
sent during specific queues opening time.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Now that we have the EST code for XGMAC and QoS we can use it with the
TAPRIO scheduler. Integrate it into the main driver and use the API to
configure the EST feature.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Adds the support for EST in XGMAC cores. This feature allows to offload
scheduling of queues opening time to the IP.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Adds the support for EST in GMAC5+ cores. This feature allows to offload
scheduling of queues opening time to the IP.
Signed-off-by: NJose Abreu <joabreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When we have pending packets we re-arm the TX timer with a magic value.

This changes the re-arm of the timer from 10us to the user-defined
coalesce value. As we support different speeds, having a magic value of
10us can be either too short or to large depending on the speed so we
let user configure it. The default value of the timer is 1ms but it can
be reconfigured by ethtool.

Changes from v1:
- Reword commit message (Jakub)
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

By using this mechanism we can get rid of the not so nice method of
scheduling TX NAPI when the RX was scheduled. No bandwidth reduction was
seen with this change.

Changes from v1:
- Remove useless comment (Jakub)
- Do not bind the TX clean to NAPI budget (Jakub)
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

DMA Capabilites have grown but the DebugFS that shows this info has not
been updated. Lets add the missing information.
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

If TX Coalesce timer is enabled we should always arm it, otherwise we
may hit the case where an interrupt is missed and the TX Queue will
timeout.

Arming the timer does not necessarly mean it will run the tx_clean()
because this function is wrapped around NAPI launcher.

Fixes: 9125cdd1 ("stmmac: add the initial tx coalesce schema")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

XGMAC supports maximum MTU that can go to 16KB. Lets add this check in
the calculation of RX buffer size.

Fixes: 7ac6653a ("stmmac: Move the STMicroelectronics driver")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The 16KB RX Buffer must also be 16 byte aligned. Fix it.

Fixes: 7ac6653a ("stmmac: Move the STMicroelectronics driver")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

We need to align the RX buffer size to at least 16 byte so that IP
doesn't mis-behave. This is required by HW.

Changes from v2:
- Align UP and not DOWN (David)

Fixes: 7ac6653a ("stmmac: Move the STMicroelectronics driver")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When switching between buffer sizes we need to clear the previous value.

Fixes: d6ddfacd ("net: stmmac: Add DMA related callbacks for XGMAC2")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Only the last received buffer contains the FCS field. Check for end of
packet before trying to strip the FCS field.

Fixes: 88ebe2cf ("net: stmmac: Rework stmmac_rx()")
Signed-off-by: NJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>