1. 01 3月, 2019 1 次提交
    • W
      drm/i915/gvt: stop scheduling workload when vgpu is inactive · 9f498477
      Weinan Li 提交于
      There is one corner case that workload_thread may pick and dispatch one
      workload of vgpu after it's already deactivated. Below is the scenario:
      
      1. deactive_vgpu got the vgpu_lock, it found pending workload was
      submitted, then it released the vgpu_lock and wait for vgpu idle.
      2. before deactive_vgpu got the vgpu_lock back, workload_thread might pick
      one new valid workload, then it was blocked by the vgpu_lock.
      3. deactive_vgpu got the vgpu_lock again, finished the last processes of
      deactivating, then release the vgpu_lock.
      4. workload_thread got the vgpu_lock, then it will try to dispatch the
      fetched workload. It's not expected one workload of deactivated vgpu is
      dispatched.
      
      The solution is to add condition check of the vgpu's active flag and stop
      to schedule when it's inactive.
      Reviewed-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NWeinan Li <weinan.z.li@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      9f498477
  2. 22 2月, 2019 1 次提交
    • C
      drm/i915/gvt: Add in context mmio 0x20D8 to gen9 mmio list · 1e8b15a1
      Colin Xu 提交于
      Depends on GEN family and I915_PARAM_HAS_CONTEXT_ISOLATION, Mesa driver
      will decide whether constant buffer 0 address is relative or absolute,
      and load GPU initial state by lri to context mmio INSTPM (GEN8)
      or 0x20D8 (>=GEN9).
      Mesa Commit fa8a764b62
      ("i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.")
      
      INSTPM is already added to gen8_engine_mmio_list, but 0x20D8 is missed
      in gen9_engine_mmio_list. From GVT point of view, different guest could
      have different context so should switch those mmio accordingly.
      
      v2: Update fixes commit ID.
      
      Fixes: 17865713 ("drm/i915/gvt: vGPU context switch")
      Reviewed-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NColin Xu <colin.xu@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      1e8b15a1
  3. 21 2月, 2019 1 次提交
    • Z
      drm/i915/gvt: Fix MI_FLUSH_DW parsing with correct index check · 13bcb80b
      Zhenyu Wang 提交于
      When MI_FLUSH_DW post write hw status page in index mode, the index
      value is in dword step and turned into address offset in cmd dword1.
      As status page size is 4K, so can't exceed that.
      
      This fixed upper bound check in cmd parser code which incorrectly
      stopped VM for reason of invalid MI_FLUSH_DW write index.
      
      v2:
      - Fix upper bound as 4K page size because index value is address offset.
      
      Fixes: be1da707 ("drm/i915/gvt: vGPU command scanner")
      Cc: stable@vger.kernel.org # v4.10+
      Cc: "Zhao, Yan Y" <yan.y.zhao@intel.com>
      Reviewed-by: NYan Zhao <yan.y.zhao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      13bcb80b
  4. 23 1月, 2019 1 次提交
  5. 15 1月, 2019 2 次提交
  6. 14 1月, 2019 1 次提交
  7. 09 1月, 2019 1 次提交
    • Z
      drm/i915/gvt: Fix workload request allocation before request add · f0e99437
      Zhenyu Wang 提交于
      In commit 6bb2a2af ("drm/i915/gvt: Fix crash after request->hw_context change"),
      forgot to handle workload scan path in ELSP handler case which was to
      optimize scanning earlier instead of in gvt submission thread, so request
      alloc and add was splitting then which is against right process.
      
      This trys to do a partial revert of that commit which still has workload
      request alloc helper and make sure shadow state population is handled after
      request alloc for target state buffer.
      
      v3: Fix missed workload status setting in request alloc error path
      v2: Fix dispatch workload err path that should add request after alloc anyway.
      
      Fixes: 6bb2a2af ("drm/i915/gvt: Fix crash after request->hw_context change")
      Cc: Bin Yang <bin.yang@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Tested-by: NBin Yang <bin.yang@intel.com>
      Reviewed-by: NXiaolin Zhang <xiaolin.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      f0e99437
  8. 05 1月, 2019 5 次提交
  9. 04 1月, 2019 7 次提交
  10. 03 1月, 2019 14 次提交
  11. 02 1月, 2019 6 次提交