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  1. 27 5月, 2012 1 次提交
  3. 18 4月, 2012 2 次提交
  5. 09 4月, 2012 1 次提交
  7. 29 3月, 2012 1 次提交
  9. 19 3月, 2012 7 次提交
  11. 17 3月, 2012 1 次提交
    • C
      firewire: ohci: fix too-early completion of IR multichannel buffers · 0c0efbac
      由 Clemens Ladisch 提交于 
      handle_ir_buffer_fill() assumed that a completed descriptor would be
indicated by a non-zero transfer_status (as in most other descriptors).
However, this field is written by the controller as soon as (the end of)
the first packet has been written into the buffer.  As a consequence, if
we happen to run into such a descriptor when the interrupt handler is
executed after such a packet has completed, the descriptor would be
taken out of the list of active descriptors as soon as the buffer had
been partially filled, so the event for the buffer being completely
filled would never be sent.

To fix this, handle descriptors only when they have been completely
filled, i.e., when res_count == 0.  (This also matches the condition
that is reported by the controller with an interrupt.)
Signed-off-by: NClemens Ladisch <clemens@ladisch.de>
Cc: 2.6.36+ <stable@vger.kernel.org>
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      0c0efbac
  13. 11 3月, 2012 2 次提交
  15. 31 1月, 2012 1 次提交
  17. 27 1月, 2012 1 次提交
  19. 16 1月, 2012 1 次提交
  21. 18 10月, 2011 2 次提交
    • C
      firewire: ohci: fix isochronous DMA synchronization · a572e688
      由 Clemens Ladisch 提交于 
      Add the dma_sync_single_* calls necessary to ensure proper cache
synchronization for isochronous data buffers on non-coherent
architectures.
Signed-off-by: NClemens Ladisch <clemens@ladisch.de>
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      a572e688
    • C
      firewire: ohci: work around selfID junk due to wrong gap count · 32eaeae1
      由 Clemens Ladisch 提交于 
      If a device's firmware initiates a bus reset by setting the IBR bit in
PHY register 1 without resetting the gap count field to 63 (and without
having sent a PHY configuration packet beforehand), the gap count of
this node will remain at the old value after the bus reset and thus be
inconsistent with the gap count on all other nodes.

The bus manager is supposed to detect the inconsistent gap count values
in the self ID packets and correct them by issuing another bus reset.

However, if the buggy device happens to be the cycle master, and if it
sends a cycle start packet immediately after the bus reset (which is
likely after a long bus reset), then the time between the end of the
selfID phase and the start of the cycle start packet will be based on
the too-small gap count value, so this gap will be too short to be
detected as a subaction gap by the other nodes.  This means that the
cycle start packet will be assumed to be self ID data, and will be
stored after the actual self ID quadlets in the self ID buffer.

This garbage in the self ID buffer made firewire-core ignore all of the
self ID data, and thus prevented the Linux bus manager from correcting
the problem.  Furthermore, because the bus reset handling was aborted
completely, asynchronous transfers would be no longer handled correctly,
and fw_run_transaction() would hang until the next bus reset.

To fix this, make the detection of inconsistent self IDs more
discriminating:  If the invalid data in the self ID buffer looks like
a cycle start packet, we can assume that the previous data in the buffer
is correctly received self ID information, and process it normally.

(We inspect only the first quadlet of the cycle start packet, because
this value is different enough from any valid self ID quadlet, and many
controllers do not store the cycle start packet in five quadlets because
they expect self ID data to have an even number of quadlets.)

This bug has been observed when a bus-powered DesktopKonnekt6 is
switched off with its power button.
Signed-off-by: NClemens Ladisch <clemens@ladisch.de>
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      32eaeae1
  23. 09 10月, 2011 3 次提交
    • S
      firewire: net: Use posted writes · a74477db
      由 Stephan Gatzka 提交于 
      Change memory region to ohci "middle address space". This effectively
reduces the number of packets by 50%.

[Stefan R.:]  This eliminates 1394 ack packets and improved throughput
by a few percent in some tests with an S400a connection with and without
gap count optimization.  Since firewire-net taxes the AR-req DMA unit of
a FireWire controller much more than firewire-sbp2 (which uses the
middle address space with PCI posted writes too), this commit also
changes a related error printk into a ratelimited one as a precaution.

Side note:  The IPv4-over-1394 drivers of Mac OS X 10.4, Windows XP SP3,
and the Thesycon 1394 bus driver for Windows all use the middle address
space too.
Signed-off-by: NStephan Gatzka <stephan@gatzka.org>
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      a74477db
    • S
      firewire: ohci: optimize TSB41BA3D detection · b810e4ae
      由 Stefan Richter 提交于 
      Takes less source code and machine code, and less runtime with PHYs
other than TSB41BA3D (e.g. TSB81BA3 with device ID 0x831304 which takes
one instead of six read_paged_phy_reg now).
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      b810e4ae
    • S
      firewire: ohci: TSB41BA3D support tweaks · 28897fb7
      由 Stefan Richter 提交于 
      Fix:  phy_reg_mutex must be held over the write/read_phy_reg pair which
gets PHY port status.

Only print to the log when a TSB41BA3D was found.  By far most TSB82AA2
cards have a TSB81BA3, and firewire-ohci can keep quiet about that.

Shorten some strings and comments.  Change some whitespace.
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      28897fb7
  25. 17 9月, 2011 3 次提交
  27. 12 8月, 2011 1 次提交
  29. 10 7月, 2011 1 次提交
  31. 09 7月, 2011 4 次提交
    • S
      firewire: ohci: skip soft reset retries after card ejection · 9f426173
      由 Stefan Richter 提交于 
      The software reset in firewire-ohci's pci_remove does not have a great
prospect of success if the card was already physically removed at this
point.  So let's skip the 500 ms that were spent in retries here.

Also, replace a defined constant by its open-coded value.  This is not a
constant from a specification but an arbitrarily chosen retry limit.  It
was only used in this single place.
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      9f426173
    • S
      firewire: ohci: fix PHY reg access after card ejection · 215fa444
      由 Stefan Richter 提交于 
      Detect and handle ejection of FireWire CardBus cards in PHY register
accesses:

  - The last attempt of firewire-core to reset the bus during shutdown
    caused a spurious "firewire_ohci: failed to write phy reg" error
    message in the log.  Skip this message as well as the prior retry
    loop that needlessly took 100 milliseconds.

  - In the unlikely case that a PHY register was read right after card
    ejection, a bogus value was obtained and possibly acted upon.
    Instead, fail the read attempt.
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      215fa444
    • S
      firewire: ohci: add a comment on PHY reg access serialization · b14c369d
      由 Stefan Richter 提交于 
      Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      b14c369d
    • S
      firewire: ohci: reduce potential context_stop latency · 9ef28ccd
      由 Stefan Richter 提交于 
      Stopping an isochronous reception DMA context takes two loop iterations
in context_stop on several controllers (JMicron, NEC, VIA).  But there
is no extra delay necessary between these two reg_read trials; the MMIO
reads themselves are slow enough.  Hence bring back the behavior from
before commit dd6254e5 "firewire: ohci:
remove superfluous posted write flushes" on these controllers by means
of an "if (i)" condition.

Isochronous context stop is performed in preemptible contexts (and only
rarely), hence this change is of little impact.  (Besides, Agere and TI
controllers always, or almost always, have the context stopped already
at the first ContextControl read.)

More important is asynchronous transmit context stop, which is performed
while local interrupts are disabled (on the two AT DMAs in
bus_reset_tasklet, i.e. after a self-ID-complete event).  In my
experience with several controllers, tested with a usermode AT-request
transmitter as well as with FTP transmission over firewire-net, the AT
contexts were luckily already stopped at the first ContextControl read,
i.e. never required another MMIO read let alone mdelay.  A possible
explanation for this is that the controllers which I tested perhaps stop
AT DMA before they perform the self-ID reception DMA.

But we cannot be sure about that and should keep the interrupts-disabled
busy loop as short as possible.  Hence, query the ContextControl
register in 1000 udelay(10) intervals instead of 10 udelay(1000)
intervals.  I understand from an estimation by Clemens Ladisch that
stopping a busy DMA context should take microseconds or at worst tens of
microseconds, not milliseconds.
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      9ef28ccd
  33. 02 6月, 2011 1 次提交
    • C
      firewire: ohci: remove superfluous posted write flushes · dd6254e5
      由 Clemens Ladisch 提交于 
      The call to flush_writes() in context_stop() is superfluous because
another register read is done immediately afterwards.

The call to flush_writes() in ar_context_run() does not need to be done
individually for each AR context, so move it to ohci_enable().  This
also makes ohci_enable() clearer because it no longer depends on a side
effect of ar_context_run() to flush its own register writes.

Finally, the setting of a context's wake bit does not need to be flushed
because neither the driver logic nor the API require the CPU to wait for
this action.  This removes the last MMIO reads from the packet queueing
code paths.
Signed-off-by: NClemens Ladisch <clemens@ladisch.de>
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      dd6254e5
  35. 11 5月, 2011 1 次提交
    • C
      firewire: optimize iso queueing by setting wake only after the last packet · 13882a82
      由 Clemens Ladisch 提交于 
      When queueing iso packets, the run time is dominated by the two
MMIO accesses that set the DMA context's wake bit.  Because most
drivers submit packets in batches, we can save much time by
removing all but the last wakeup.

The internal kernel API is changed to require a call to
fw_iso_context_queue_flush() after a batch of queued packets.
The user space API does not change, so one call to
FW_CDEV_IOC_QUEUE_ISO must specify multiple packets to take
advantage of this optimization.

In my measurements, this patch reduces the time needed to queue
fifty skip packets from userspace to one sixth on a 2.5 GHz CPU,
or to one third at 800 MHz.
Signed-off-by: NClemens Ladisch <clemens@ladisch.de>
Signed-off-by: NStefan Richter <stefanr@s5r6.in-berlin.de>
      13882a82
  37. 03 5月, 2011 1 次提交
    • B
      firewire: Fix for broken configrom updates in quick succession · 2e053a27
      由 B.J. Buchalter 提交于 
      Current implementation of ohci_set_config_rom() uses a deferred
bus reset via fw_schedule_bus_reset(). If clients add multiple
unit descriptors to the config_rom in quick succession, the
deferred bus reset may not have fired before succeeding update
requests have come in. This can lead to an incorrect partial
update of the config_rom for both addition and removal of
config_rom descriptors, as the ohci_set_config_rom() routine
will return -EBUSY if a previous pending update has not been
completed yet; the requested update just gets dropped on the floor.

This patch recognizes that the "in-flight" update can be modified
until it has been processed by the bus-reset, and the locking
in the bus_reset_tasklet ensures that the update is done atomically
with respect to modifications made by ohci_set_config_rom(). The
-EBUSY error case is simply removed.

[Stefan R:  The bug always existed at least theoretically.  But it
became easy to trigger since 2.6.36 commit 02d37bed "firewire: core:
integrate software-forced bus resets with bus management" which
introduced long mandatory delays between janitorial bus resets.]
Signed-off-by: NBenjamin Buchalter <bj@mhlabs.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> (trivial style changes)
Cc: <stable@kernel.org> # 2.6.36.y and newer
      2e053a27
  39. 20 4月, 2011 3 次提交
  41. 15 3月, 2011 2 次提交