Check the overrides in the firmware info table before
enabling spread spectrum on the engine or memory clocks.

Some boards may have valid spread spectrum tables, but
shouldn't necessarily have it enabled.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No support for reading temperature back yet.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for DPM on CIK.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For correctness.  The fb divider isn't actually used
in any of the relevant dpm code.  It's calculated
from the other parameters.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

It seems gcc 4.8.1 generates bogus code for the old logic causing
part of the function to get skipped.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Parsing the table in incorrectly led to problems with
certain asics with mclk switching.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.

This improves the out of the box performance with SI asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Bad pointer math.  Fixes hangs in state transitions with
BTC+ asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The arrays items are variable sized.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add a way to look up the bootup mvdd.  Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Validate the voltages against the voltage requirements of the
dispclk.  We currently don't adjust the disp clock so it never
changes, but we need to filter out voltage levels that are too
low none the less.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SI uses a new atom table revision.  Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SI uses a new atom table.  Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There's a new table for calculating the memory pll
parameters on SI.  Required for SI DPM support.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for rv6xx asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching

Set radeon.dpm=1 to enable.

v2: remove duplicate line
v3: fix thermal interrupt check noticed by Jerome
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

dpm needs access to atombios data and command tables
for setup and calculation of a number of parameters.

v2: endian fix
v3: fix mc reg table bug
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

CIK uses a slightly different variant of the table structs
and params.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SI uses v5 of the command table and uses a different table
for memory PLLs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No support for reading the temperature yet.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The code was mis-handling variable sized arrays.
Reported-by: NSylvain BERTRAND <sylware@legeek.net>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

We actually care about the chip family rather than the
DCE version although functionally they are the same.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If we have a empty power table, bail early and allocate
the default power state.

Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=63865Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

v2: fix copy paste typo.
v3: clarify new union member
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Convert #include "..." to #include <path/...> in drivers/gpu/.
Signed-off-by: NDavid Howells <dhowells@redhat.com>
Acked-by: NDave Airlie <airlied@redhat.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: NDave Jones <davej@redhat.com>

Don't read past the end of the array if we encounter an unknown
thermal controller.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

A table in the vbios tells us whether the GPU backlight controller
is used or not.  If the bit is set, the GPU backlight controller is
used; if it is not set, an off-chip backlight controller is used.

v2: store all the firmware flags, not just BL control
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There is a more recent APU stepping with a new PCI ID
shipping in the same board by Fujitsu which needs the
same quirk to correctly mark the back plane connectors.
Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@onelan.co.uk>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

The IntegratedSystemInfo table changed versions
on TN.  Update the SS override lookup to handle it.

v2: fix copy-paste typo.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>