This introduces a new top level config symbol ARM_SINGLE_ARMV7M
for non-MMU, ARMv7-M platforms. It also support multiple ARMv7-M
platforms in one kernel image since the cores share the same
basic memory layout and interrupt controller. However, this works
only if the combined platforms also have a similar (main) memory
layout.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Remove the needless differences between MMU/!MMU addruart calls.
This allows to use the same addruart macro on SoC level. Useful
for SoC consisting of multiple CPUs with and without MMU such as
Freescale Vybrid.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This makes uniphier behave like all the other platforms that
support TWD, and only select this driver when SMP is enabled.
Without this, we get a compile error on UP builds:

arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register':
arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function)
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Using a dedicated symbol for low-level debugging instead of the
arch symbol will make this platform play nice when enabled on a
kernel that supports multiple platforms.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The SLCR is unconditionally unlocked early on boot in zynq_slcr_init()
and not ever re-locked. As such, it is not necessary to explicitly unlock in
the restart codepath.
Signed-off-by: NJosh Cartwright <joshc@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.

Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: NJosh Cartwright <joshc@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Bring up the secondary core. Enable hotplug with supporting
powering off secondary core.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Use the UART0 peripheral for low level debug. Only the UART port 0 is
currently supported.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add basic code for ZTE ZX296702 platform.

[arnd: removed unused zx296702_init_machine function, and changed
       l2c aux val to default]
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4)
SoCs. These SoCs are NXP's high preformance MCU line and can run at
clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx.

LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few
extra peripherals. The LPC43xx series also features one or two
Cortex-M0 cores that can be used to offload the main M4 core.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Reviewed-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Since the WDT is what's used to drive restart and power off, it makes
more sense to keep it there, where the regs are already mapped and
definitions for them provided.  Note that this means you may need to
add CONFIG_BCM2835_WDT to retain functionality of your kernel.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This is the default function that gets called if the hook is NULL.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The only thing we were using this 16MB mapping of IO peripherals for
was the uart's early debug mapping.  If we just drop the map_io hook,
the kernel will call debug_ll_io_init() for us, which maps the single
page needed for the device.
Signed-off-by: NEric Anholt <eric@anholt.net>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove
map_io in socfpga.c.

Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is
already doing the CPU mapping.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.

This is the last step of clock framework transition for pxa
platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and
zylonite (pxa3xx).
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

As pxa architecture transitions to clock framework, the previously
available INIT_CLKREG is no more. Use the fixed clock rate initializer
to declare the "fake" CLK_CK32K in eseries.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

Transition the PXA25x and PXA27x CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.

The transition breaks the previous clocks activation of pin
control (gpio11 and gpio12). Machine files should be amended to take
that into account.

This is the last step of clock framework transition for pxa25x and
pxa27x, leaving only pxa3xx for further work.
Reviewed-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

When booting via DT, the default PXA devices must not have been probed
before, otherwise the augmented information from the device tree is
ignored.

This is the twin commit of commit 82ce44d1 ("ARM: pxa3xx: skip
default device initialization when booting via DT").
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Acked-by: NDaniel Mack <daniel@zonque.org>

The pxa25x gpio11 clock output was previously selected on its pin by the
clock enabling, toggling the pin function.

As we transition to common clock framework, the pin function is moved to
board file for the 2 users, ie. lubbock and eseries.
Reviewed-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

Since pxa clocks were ported to the clock framework, an ordering issue
appears between clocks and clocksource initialization. As a consequence,
the pxa timer clock cannot be acquired in pxa_timer, and is disabled by
clock framework because it is "unused".

The ordering issue is that in the kernel boot sequence :
  start_kernel()
    ...
    time_init()
      -> pxa_timer()
        -> here the clocksource is initialized
    ...
    rest_init()
      kernel_init()
	initcalls
	  -> here the clocks are initialized

In the current sequence, the clocks are initialized way after pxa_timer,
which cannot acquire the OSTIMER0 clock.

To solve this issue, the clocks initialization is moved to pxa_timer(),
so that clocks are initialized before clocksource for non device-tree.
For device-tree, the standard arm time_init() will take care of the
ordering.
Reviewed-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

Initial commit for a new SoC family, UniPhier, developed by
Socionext Inc. (formerly, System LSI Business Division of
Panasonic Corporation).

This commit includes a minimal set of components for booting the
kernel, including SMP support.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

All the necessary debug uart mapping is already being done in
debug_ll_io_init, there's no need for it here.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Add support for hardware uart1 for earlyprintk support on Arria10 devkit.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Now the debug and platsmp.S are fixed for big endian, the
architecture can now advertise big endian support.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Update the secondary code to allow the secondary boot to work when the
system is running big endian.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

If the 8250 debug code is used in word mode on an big endian
host then the writes need to be change into little endian for
the bus.

Note, we have to re-convert the value back as the debug code
will inspect the value after writing it to see if a newline
has been written.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

The Marvell mwifiex driver prevents the system to enter into a suspend
state if the card power is not preserved during a suspend/resume cycle.

So Suspend-to-RAM and Suspend-to-idle are failing on Exynos5250 Snow.

Add the keep-power-in-suspend Power Management property to the SDIO/MMC
node so the mwifiex suspend handler doesn't fail and the system is able
to enter into a suspend state.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Remove the extra zero in the "cpu-crit-0" trip point for exynos5420
and exynos5440.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The Exynos4412 SoC has a s3c6410 RTC where the source clock
is now a mandatory property.
This patch fixes probe failure of s3c-rtc on Odroid-X2/U2/U3 boards.
Signed-off-by: NMarkus Reichl <m.reichl@fivetechno.de>
Tested-by: NTobias Jakobi <tjakobi@math.uni-bielefeld.de>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Commit ea08de16 ("ARM: dts: Add DISP1 power domain for exynos5420")
added a device node for the Exynos5420 DISP1 power domain but dit not
make the DP controller a consumer of that power domain.

This causes an "Unhandled fault: imprecise external abort" error if the
exynos-dp driver tries to access the DP controller registers and the PD
was turned off. This lead to a kernel panic and a complete system hang.

Make the DP controller device node a consumer of the DISP1 power domain
to ensure that the PD is turned on when the exynos-dp driver is probed.

Fixes: ea08de16 ("ARM: dts: Add DISP1 power domain for exynos5420")
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Select IMX50, IMX6SX and LS1021A SoC support.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Make sure that xen_swiotlb_init allocates buffers that are DMA capable
when at least one memblock is available below 4G. Otherwise we assume
that all devices on the SoC can cope with >4G addresses. We do this on
ARM and ARM64, where dom0 is mapped 1:1, so pfn == mfn in this case.

No functional changes on x86.

From: Chen Baozi <baozich@gmail.com>
Signed-off-by: NChen Baozi <baozich@gmail.com>
Signed-off-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
Tested-by: NChen Baozi <baozich@gmail.com>
Acked-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: NDavid Vrabel <david.vrabel@citrix.com>

The L3 Error handling on OMAP5 for the most part is very similar
to that of OMAP4, and had leveraged common data structures and
register layout definitions so far. Upon closer inspection, there
are a few minor differences causing an incorrect decoding and
reporting of the master NIU upon an error:

  1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies
     11 bits on OMAP5 as against 8 bits on OMAP4, with the master
     NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR
     field.
  2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3
     input sources on OMAP5. The common DEBUGSS source is at a
     different input on each SoC.

Fix the above issues by using a OMAP5-specific compatible property
and using SoC-specific data where there are differences.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Fix a typo in DRA7 dtsi where 12 bytes are needed for register
description of ABB efuse registers, however only 8 bytes are provided
to map. For some weird reason, this does not generate abort at offset
0x8, probably due to default maps already provided in io.c for the bus
register ranges.
Reported-by: NMatt Gessner <Matt.Gessner@windriver.com>
Reported-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

BeagleBoard-X15 pre-production change includes switching the GPIO fan
gpio over from 1 to 2 to allow for a potential fix at a later point in
time for USB client VBUS detection using PMIC VBUS detect capability.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

BeagleBoard-X15 pre-production change includes switching over to UART
pins that now allow for UART download capability. All original boards
should either have been returned for modifications or already modified
for the required change and maintaining compatibility for older boards
are no longer needed.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The new AM437x SK Beta boards have removed the
large capacitors on the gpio-matrix column lines
which means we can reduce col-scan-delay-us to 5us
without loosing functionality.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

AM437x Starter Kit uses a NewHaven Display module with
a 4.3" display and EDT FT5306 touchscreen

On that module's new revision, NewHave decided to change
the pinout on the 6 pin flat-pcb touchscreen connector so
that instead of having WAKE pin, we now have RESETn.

The new display module is available on AM437x SK Beta and
all new revisions while the older revision is only available
on AM437x SK Alpha which, unfortunately, can't be supported
anymore in mainline without a revert of this patch.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>