1. 09 2月, 2017 16 次提交
  2. 03 2月, 2017 3 次提交
  3. 31 1月, 2017 1 次提交
  4. 30 1月, 2017 1 次提交
    • A
      stmmac: Discard masked flags in interrupt status register · 0a764db1
      Alexey Brodkin 提交于
      DW GMAC databook says the following about bits in "Register 15 (Interrupt
      Mask Register)":
      --------------------------->8-------------------------
      When set, this bit __disables_the_assertion_of_the_interrupt_signal__
      because of the setting of XXX bit in Register 14 (Interrupt
      Status Register).
      --------------------------->8-------------------------
      
      In fact even if we mask one bit in the mask register it doesn't prevent
      corresponding bit to appear in the status register, it only disables
      interrupt generation for corresponding event.
      
      But currently we expect a bit different behavior: status bits to be in
      sync with their masks, i.e. if mask for bit A is set in the mask
      register then bit A won't appear in the interrupt status register.
      
      This was proven to be incorrect assumption, see discussion here [1].
      That misunderstanding causes unexpected behaviour of the GMAC, for
      example we were happy enough to just see bogus messages about link
      state changes.
      
      So from now on we'll be only checking bits that really may trigger an
      interrupt.
      
      [1] https://lkml.org/lkml/2016/11/3/413Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Fabrice Gasnier <fabrice.gasnier@st.com>
      Cc: Joachim Eastwood <manabian@gmail.com>
      Cc: Phil Reid <preid@electromag.com.au>
      Cc: David Miller <davem@davemloft.net>
      Cc: Alexandre Torgue <alexandre.torgue@gmail.com>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0a764db1
  5. 25 1月, 2017 1 次提交
  6. 23 1月, 2017 1 次提交
  7. 19 1月, 2017 1 次提交
  8. 18 1月, 2017 1 次提交
    • J
      stmmac: add missing of_node_put · a249708b
      Julia Lawall 提交于
      The function stmmac_dt_phy provides several possibilities for initializing
      plat->mdio_node, all of which have the effect of increasing the reference
      count of the assigned value.  This field is not updated elsewhere, so the
      value is live until the end of the lifetime of plat (devm_allocated), just
      after the end of stmmac_remove_config_dt.  Thus, add an of_node_put on
      plat->mdio_node in stmmac_remove_config_dt.  It is possible that the field
      mdio_node is never initialized, but of_node_put is NULL-safe, so it is also
      safe to call of_node_put in that case.
      Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
      Acked-by: NAlexandre TORGUE <alexandre.torgue@st.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a249708b
  9. 17 1月, 2017 1 次提交
  10. 16 1月, 2017 1 次提交
  11. 10 1月, 2017 3 次提交
  12. 09 1月, 2017 1 次提交
  13. 03 1月, 2017 4 次提交
  14. 30 12月, 2016 3 次提交
  15. 28 12月, 2016 2 次提交
    • F
      net: stmmac: Fix race between stmmac_drv_probe and stmmac_open · 57016590
      Florian Fainelli 提交于
      There is currently a small window during which the network device registered by
      stmmac can be made visible, yet all resources, including and clock and MDIO bus
      have not had a chance to be set up, this can lead to the following error to
      occur:
      
      [  473.919358] stmmaceth 0000:01:00.0 (unnamed net_device) (uninitialized):
                      stmmac_dvr_probe: warning: cannot get CSR clock
      [  473.919382] stmmaceth 0000:01:00.0: no reset control found
      [  473.919412] stmmac - user ID: 0x10, Synopsys ID: 0x42
      [  473.919429] stmmaceth 0000:01:00.0: DMA HW capability register supported
      [  473.919436] stmmaceth 0000:01:00.0: RX Checksum Offload Engine supported
      [  473.919443] stmmaceth 0000:01:00.0: TX Checksum insertion supported
      [  473.919451] stmmaceth 0000:01:00.0 (unnamed net_device) (uninitialized):
                      Enable RX Mitigation via HW Watchdog Timer
      [  473.921395] libphy: PHY stmmac-1:00 not found
      [  473.921417] stmmaceth 0000:01:00.0 eth0: Could not attach to PHY
      [  473.921427] stmmaceth 0000:01:00.0 eth0: stmmac_open: Cannot attach to
                      PHY (error: -19)
      [  473.959710] libphy: stmmac: probed
      [  473.959724] stmmaceth 0000:01:00.0 eth0: PHY ID 01410cc2 at 0 IRQ POLL
                      (stmmac-1:00) active
      [  473.959728] stmmaceth 0000:01:00.0 eth0: PHY ID 01410cc2 at 1 IRQ POLL
                      (stmmac-1:01)
      [  473.959731] stmmaceth 0000:01:00.0 eth0: PHY ID 01410cc2 at 2 IRQ POLL
                      (stmmac-1:02)
      [  473.959734] stmmaceth 0000:01:00.0 eth0: PHY ID 01410cc2 at 3 IRQ POLL
                      (stmmac-1:03)
      
      Fix this by making sure that register_netdev() is the last thing being done,
      which guarantees that the clock and the MDIO bus are available.
      
      Fixes: 4bfcbd7a ("stmmac: Move the mdio_register/_unregister in probe/remove")
      Reported-by: NKweh, Hock Leong <hock.leong.kweh@intel.com>
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      57016590
    • K
      net: stmmac: fix incorrect bit set in gmac4 mdio addr register · 5799fc90
      Kweh, Hock Leong 提交于
      Fixing the gmac4 mdio write access to use MII_GMAC4_WRITE only instead of
      OR together with MII_WRITE.
      Signed-off-by: NKweh, Hock Leong <hock.leong.kweh@intel.com>
      Acked-By: NJoao Pinto <jpinto@synopsys.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5799fc90