- 03 6月, 2010 1 次提交
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由 Luis R. Rodriguez 提交于
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 12 5月, 2010 1 次提交
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由 Luis R. Rodriguez 提交于
These changes include: * For PAPRD, the TXRF3.capdiv5G, TXRF3.rdiv5G and TXRF3.rdiv2G are set to 0x0, the TXRF6.capdiv2G is set to 0x2 for all three chains. * The d2cas5G/d3cas5G/d4cas5G was updated to 4/4/4 in lowest_ob_db Tx gain table. * To improve DPPM, three parameters were updated (Released from Madhan): 1. RANGE_OSDAC is set to 0x1 for 2G, 0x0 for 5G 2. offsetC1 is set to 0xc 3. inv_clk320_adc is set to 0x1 * To reduce PHY error(from spur), cycpwr_thr1 and cycpwr_thr1_ext are increased to 0x8 at 2G. * The 2G Rx gain tables are updated with mixer gain setting 3,1,0. The new checksums yield: initvals -f ar9003 0x00000000c2bfa7d5 ar9300_2p0_radio_postamble 0x00000000ada2b114 ar9300Modes_lowest_ob_db_tx_gain_table_2p0 0x00000000e0bc2c84 ar9300Modes_fast_clock_2p0 0x00000000056eaf74 ar9300_2p0_radio_core 0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p0 0x0000000078658fb5 ar9300_2p0_mac_postamble 0x0000000023235333 ar9300_2p0_soc_postamble 0x0000000054d41904 ar9200_merlin_2p0_radio_core 0x00000000748572cf ar9300_2p0_baseband_postamble 0x000000009aa5a0a4 ar9300_2p0_baseband_core 0x000000003df9a326 ar9300Modes_high_power_tx_gain_table_2p0 0x000000001cfba124 ar9300Modes_high_ob_db_tx_gain_table_2p0 0x0000000011302700 ar9300Common_rx_gain_table_2p0 0x00000000e3eab114 ar9300Modes_low_ob_db_tx_gain_table_2p0 0x00000000c9d66d40 ar9300_2p0_mac_core 0x000000001e1d0800 ar9300Common_wo_xlna_rx_gain_table_2p0 0x00000000a0c54980 ar9300_2p0_soc_preamble 0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0 0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p0 0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p0 Cc: Don Breslin <don.breslin@atheros.com> Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 08 5月, 2010 1 次提交
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由 Luis R. Rodriguez 提交于
Generated using the new shiny intivals-tool [1]: initvals -w -f ar9003 > ar9003_initvals.h The respective checksums are: 0x000000005a76829d ar9300_2p0_radio_postamble 0x000000009d90cb74 ar9300Modes_lowest_ob_db_tx_gain_table_2p0 0x00000000e0bc2c84 ar9300Modes_fast_clock_2p0 0x00000000852fca34 ar9300_2p0_radio_core 0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p0 0x0000000078658fb5 ar9300_2p0_mac_postamble 0x0000000023235333 ar9300_2p0_soc_postamble 0x0000000054d41904 ar9200_merlin_2p0_radio_core 0x00000000618455d4 ar9300_2p0_baseband_postamble 0x000000009aa590a4 ar9300_2p0_baseband_core 0x000000004783d946 ar9300Modes_high_power_tx_gain_table_2p0 0x000000006681db44 ar9300Modes_high_ob_db_tx_gain_table_2p0 0x000000001f318700 ar9300Common_rx_gain_table_2p0 0x000000009990cb74 ar9300Modes_low_ob_db_tx_gain_table_2p0 0x00000000c9d66d40 ar9300_2p0_mac_core 0x0000000039139500 ar9300Common_wo_xlna_rx_gain_table_2p0 0x00000000a0c54980 ar9300_2p0_soc_preamble 0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0 0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p0 0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p0 [1] http://wireless.kernel.org/en/users/Drivers/ath9k_hw/initvals-tool Cc: Tom Hammel <thammel@atheros.com> Cc: Enis Akay <Enis.Akay@Atheros.com> Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 28 4月, 2010 1 次提交
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由 Felix Fietkau 提交于
This synchs up the initvals to the values used on the Atheros HAL for AR9003. This specific change adds support for a new high power module. Signed-off-by: NFelix Fietkau <nbd@openwrt.org> Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 17 4月, 2010 1 次提交
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由 Luis R. Rodriguez 提交于
The AR9003 hardware family now initializes hardware by block components and into stages: pre, core and init. Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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