Use tegra124_(primary|overlay)_formats for Tegra124, otherwise the count
specified in the Tegra124 SoC info structure will be different from the
array size and cause a crash.

Fixes: 511c7023 ("drm/tegra: dc: Support more formats")
Signed-off-by: NStefan Agner <stefan@agner.ch>
Acked-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Since commit 846c7dfc ("drm/atomic: Try to preserve the crtc enabled
state in drm_atomic_remove_fb, v2."), removing the last framebuffer will
no longer disable the corresponding pipeline, which causes the KMS core
to complain about leaked connectors on driver unbind.

Fix this by calling drm_atomic_helper_shutdown() on driver unbind, which
will cause all display pipelines to be shut down and therefore drop the
extra references on the connectors.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The regulator is controlled as part of runtime PM, so it should not be
additionally disabled from the ->exit() callback.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Detaching from an IOMMU group multiple times can lead to a crash. This
could potentially be fixed in the IOMMU driver, but it's easy to avoid
the subsequent detach operations in this driver, so do that as well.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Keep old 'dependent' state of unaffected planes, this way new state takes
into account current state of unaffected planes.

Fixes: ebae8d07 ("drm/tegra: dc: Implement legacy blending")
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The opaque/alpha format conversion code is currently only looking at
XRGB formats because they have an equivalent ARGB format. The opaque
format for RGB565 is RGB565 itself, much like the YUV formats map to
themselves.
Reported-by: NDmitry Osipenko <digetx@gmail.com>
Fixes: ebae8d07 ("drm/tegra: dc: Implement legacy blending")
Signed-off-by: NThierry Reding <treding@nvidia.com>

The SOR0 found on Tegra124 and Tegra210 only supports eDP and LVDS and
therefore has a slightly different clock tree than the SOR1 which does
not support eDP, but HDMI and DP instead.

Commit e1335e2f ("drm/tegra: sor: Reimplement pad clock") breaks
setups with eDP because the sor->clk_out clock is uninitialized and
therefore setting the parent clock (either the safe clock or either of
the display PLLs) fails, which can cause hangs later on since there is
no clock driving the module.

Fix this by falling back to the module clock for sor->clk_out on those
setups. This guarantees that the module will always be clocked by an
enabled clock and hence prevents those hangs.

Fixes: e1335e2f ("drm/tegra: sor: Reimplement pad clock")
Reported-by: NGuillaume Tucker <guillaume.tucker@collabora.com>
Tested-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The first overlay plane can leak if initialization of the second overlay
plane fails. Fix this by properly destroying the first overlay plane on
error.
Suggested-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Cursor and overlay planes use a possible_crtcs mask based on the DC pipe
number. However, DRM requires each bit in the mask to correspond to the
index of the CRTC, which will be different from the DC pipe number for a
configuration where the first display controller is disabled, or where a
deferred probe leads to the first display controller being probed after
the first.
Suggested-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit ebae8d07 ("drm/tegra: dc: Implement legacy blending") broke
support for YUV overlays by accident. The reason is that YUV formats are
considered opaque because they have no alpha component, but on the other
hand no corresponding format with an alpha component can be returned. In
the case of YUV formats, the opaque format is the same as the alpha
format, so add the special case to restore YUV overlay support.
Reported-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This implements alpha blending on legacy display controllers (Tegra20,
Tegra30 and Tegra114). While it's theoretically possible to support the
zpos property to enable userspace to specify the Z-order of each plane
individually, this is not currently supported and the same fixed Z-
order as previously defined is used.

Reverts commit 71835caa ("drm/tegra: fb: Force alpha formats") since
the opaque formats are now supported.
Reported-by: NDmitry Osipenko <digetx@gmail.com>
Fixes: 7772fdae ("drm/tegra: Support ARGB and ABGR formats")
Signed-off-by: NThierry Reding <treding@nvidia.com>

host1x_syncpt_wait() takes timeout value in jiffies, but DRM passes it in
milliseconds.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

iommu_map_sg() doesn't return a error value, but a size of the requested
IOMMU mapping or zero in case of error.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Hardware reset isn't actually broken on Tegra20, but there is a
dependency on the first display controller to be taken out of reset for
the second to be enabled successfully. Model this dependency using a PM
device link.
Signed-off-by: NDmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: minor cleanups, extend commit message]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The new debugfs registration fails to build when CONFIG_DEBUGFS is
disabled, because the drm_crtc structure is lacking a member in that
configuration:

drivers/gpu/drm/tegra/dc.c: In function 'tegra_dc_late_register':
drivers/gpu/drm/tegra/dc.c:1204:28: error: 'struct drm_crtc' has no member named 'debugfs_entry'

Without CONFIG_DEBUGFS, the rest of the function already degrades
into nothing, so we just avoid the one assignment.

Fixes: b95800ee ("drm/tegra: dc: Register debugfs in ->late_register()")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Keep the reset values for the common mode voltage, output driver
impedance control and output driver current control parameters. This
fixes errors seen during SCDC communication with HDMI sinks.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The newly introduced driver has optional suspend/resume functions,
causing a warning when CONFIG_PM is disabled:

drivers/gpu/drm/tegra/hub.c:749:12: error: 'tegra_display_hub_resume' defined but not used [-Werror=unused-function]
drivers/gpu/drm/tegra/hub.c:733:12: error: 'tegra_display_hub_suspend' defined but not used [-Werror=unused-function]

This marks them __maybe_unused to shut up the warnings.

Fixes: c4755fb9 ("drm/tegra: Add Tegra186 display hub support")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

In order to support IOMMUs more generically and transparently handle the
ARM SMMU on Tegra186, move to using groups instead of devices for domain
attachment. An IOMMU group is a set of devices that share the same IOMMU
domain and is therefore a good match to represent what Tegra DRM needs.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement the standard zpos property for planes on Tegra124 and later.
Earlier generations have a different blending unit that needs different
programming.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The spinlock is only used to serialize accesses to the DC_CMD_INT_MASK
register. However, this register is accesses either with interrupts
masked (in tegra_crtc_atomic_enable()) or protected by the vbl_lock and
vblank_time_lock spinlocks of the DRM device. Therefore, these accesses
don't need any extra serialization and the lock can be removed.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Traditionally, windows were accessed indirectly, through a register
selection window that required a global register to be programmed with
the index of the window to access. Since the global register could be
written from modesetting functions as well as the interrupt handler
concurrently, accesses had to be serialized using a lock. Using direct
accesses to the window registers the lock can be avoided.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Also, split up formats into per-SoC lists because not all generations
support all of them. Note that the list is now exhaustive for all RGB
formats, but not for YUV and indexed formats.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra20 and Tegra30 don't actually support the 24-bit RGB formats that
don't have an alpha component. In order to allow the fbdev emulation to
run on those chips, force the 32-bit RGBA formats.
Signed-off-by: NThierry Reding <treding@nvidia.com>

DPAUX is the same as on previous generations. Supporting it is as simple
as adding the compatible string so that the driver will bind to any of
the devices.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Move clock and reset management into runtime PM callbacks and hook them
up. This cleans up the code structure so that power management code does
not clutter up the rest.
Signed-off-by: NThierry Reding <treding@nvidia.com>

In addition to using the SCDC helpers to enable support for scrambling
for HDMI 2.0 modes, take into account the high pixel clocks when
programming some of the registers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The SOR found on Tegra186 is very similar to the one found on Tegra210
and earlier. However, due to some changes in the display architecture,
some programming sequences have changed and some register have moved
around.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Future Tegra generations have an increased number of display controllers
that can drive individual SORs. In order to support that, the offset and
layout of some registers has changed in backwards-incompatible ways. Use
parameterized register offsets to support this.
Signed-off-by: NThierry Reding <treding@nvidia.com>

These formats can easily be supported on all generations of Tegra.

Note that the XRGB and XBGR formats that we supported were in fact using
the ARGB and ABGR Tegra formats. This happened to work in cases where no
alpha was being considered. This change is also a fix for those formats.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The display architecture has changed in several signifcant ways with the
new Tegra186 SoC. Display controllers are a completely different design,
but have been given a frontend that simulates the register interface for
earlier chips.

Unfortunately the frontend isn't completely backwards compatible, so the
driver needs parameterization to take the changes into account.

One big change is that the total number of display controllers has been
increased to three. At the same time the number of planes available has
remained constant. However, planes can now be freely assigned between
the display controllers, giving applications more flexibility in making
the best use of the available resources.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The display architecture has changed in several significant ways with
the new Tegra186 SoC. Shared between all display controllers is a set
of common resources referred to as the display hub. The hub generates
accesses to memory and feeds them into various composition pipelines,
each of which being a window that can be assigned to arbitrary heads.

Atomic state is subclassed in order to track the global bandwidth
requirements and select and adjust the hub clocks appropriately. The
plane code is shared to a large degree with earlier SoC generations,
except where the programming differs.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Subsequent patches will add support for Tegra186 which has a different
architecture and needs different plane code but which can share a lot of
code with earlier Tegra support.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Move the display controller state definition to the header file so that
it can be referenced by other files.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Both tegra_overlay_plane_funcs is identical to tegra_plane_funcs. Get
rid of the duplicate and use one set of function pointers for all
planes.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This function is a simple wrapper around tegra_plane_destroy(), so it
can be dropped.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Both tegra_primary_plane_funcs and tegra_cursor_plane_funcs are
identical. Get rid of the duplicate and use one set of function pointers
for all planes.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This function is a simple wrapper around tegra_plane_destroy(), so it
can be dropped.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra display hardware has GO bits and meets all the requirements to use
drm_crtc_arm_vblank_event(). Use it instead and get rid of the hand-
rolled implementation.
Signed-off-by: NThierry Reding <treding@nvidia.com>

There's no reason not to use them, and they already get all the
semantics right, so rip out all of the custom code and replace it by the
helpers.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Starting with Tegra124, the interface to set the background color (the
value generated for pixels that are not sourced from any window) is via
a different register. Earlier generations called this the border color.
Reverse the feature flag and assume that IP revisions that don't have
support for background color will support border color instead.
Signed-off-by: NThierry Reding <treding@nvidia.com>