1. 11 2月, 2010 2 次提交
    • D
      drm/i915: Update write_domains on active list after flush. · 99fcb766
      Daniel Vetter 提交于
      Before changing the status of a buffer with a pending write we will await
      upon a new flush for that buffer. So we can take advantage of any flushes
      posted whilst the buffer is active and pending processing by the GPU, by
      clearing its write_domain and updating its last_rendering_seqno -- thus
      saving a potential flush in deep queues and improves flushing behaviour
      upon eviction for both GTT space and fences.
      
      In order to reduce the time spent searching the active list for matching
      write_domains, we move those to a separate list whose elements are
      the buffers belong to the active/flushing list with pending writes.
      
      Orignal patch by Chris Wilson <chris@chris-wilson.co.uk>, forward-ported
      by me.
      
      In addition to better performance, this also fixes a real bug. Before
      this changes, i915_gem_evict_everything didn't work as advertised. When
      the gpu was actually busy and processing request, the flush and subsequent
      wait would not move active and dirty buffers to the inactive list, but
      just to the flushing list. Which triggered the BUG_ON at the end of this
      function. With the more tight dirty buffer tracking, all currently busy and
      dirty buffers get moved to the inactive list by one i915_gem_flush operation.
      
      I've left the BUG_ON I've used to prove this in there.
      
      References:
        Bug 25911 - 2.10.0 causes kernel oops and system hangs
        http://bugs.freedesktop.org/show_bug.cgi?id=25911
      
        Bug 26101 - [i915] xf86-video-intel 2.10.0 (and git) triggers kernel oops
                    within seconds after login
        http://bugs.freedesktop.org/show_bug.cgi?id=26101Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Tested-by: NAdam Lantos <hege@playma.org>
      Cc: stable@kernel.org
      Signed-off-by: NEric Anholt <eric@anholt.net>
      99fcb766
    • Z
      drm/i915: Rework DPLL calculation parameters for Ironlake · b91ad0ec
      Zhenyu Wang 提交于
      Got Ironlake DPLL parameter table, which reflects the hardware
      optimized values. So this one trys to list DPLL parameters for
      different output types, should potential fix clock issue seen
      on new Arrandale CPUs.
      
      This fixes DPLL setting failure on one 1920x1080 dual channel
      LVDS for Ironlake. Test has also been made on LVDS panels with
      smaller size and CRT/HDMI/DP ports for different monitors on
      their all supported modes.
      
      Update:
      - Change name of double LVDS to dual LVDS.
      - Fix SSC 120M reference clock to use the right range.
      
      Cc: CSJ <changsijay@gmail.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      b91ad0ec
  2. 10 2月, 2010 14 次提交
  3. 09 2月, 2010 24 次提交