1. 06 1月, 2011 1 次提交
  2. 05 1月, 2011 5 次提交
    • H
      x86, NMI: Add touch_nmi_watchdog to io_check_error delay · 74d91e3c
      Huang Ying 提交于
      Prevent the long delay in io_check_error making NMI watchdog
      timeout.
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      Signed-off-by: NDon Zickus <dzickus@redhat.com>
      LKML-Reference: <1294198689-15447-3-git-send-email-dzickus@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      74d91e3c
    • D
      x86: Avoid calling arch_trigger_all_cpu_backtrace() at the same time · 554ec063
      Dongdong Deng 提交于
      The spin_lock_debug/rcu_cpu_stall detector uses
      trigger_all_cpu_backtrace() to dump cpu backtrace.
      Therefore it is possible that trigger_all_cpu_backtrace()
      could be called at the same time on different CPUs, which
      triggers and 'unknown reason NMI' warning. The following case
      illustrates the problem:
      
            CPU1                    CPU2                     ...   CPU N
                             trigger_all_cpu_backtrace()
                             set "backtrace_mask" to cpu mask
                                     |
      generate NMI interrupts  generate NMI interrupts       ...
          \                          |                               /
           \                         |                              /
      
      The "backtrace_mask" will be cleaned by the first NMI interrupt
      at nmi_watchdog_tick(), then the following NMI interrupts
      generated by other cpus's arch_trigger_all_cpu_backtrace() will
      be taken as unknown reason NMI interrupts.
      
      This patch uses a test_and_set to avoid the problem, and stop
      the arch_trigger_all_cpu_backtrace() from calling to avoid
      dumping a double cpu backtrace info when there is already a
      trigger_all_cpu_backtrace() in progress.
      Signed-off-by: NDongdong Deng <dongdong.deng@windriver.com>
      Reviewed-by: NBruce Ashfield <bruce.ashfield@windriver.com>
      Cc: fweisbec@gmail.com
      LKML-Reference: <1294198689-15447-2-git-send-email-dzickus@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NDon Zickus <dzickus@redhat.com>
      554ec063
    • D
      x86: Only call smp_processor_id in non-preempt cases · 9ab181fa
      Don Zickus 提交于
      There are some paths that walk the die_chain with preemption on.
      Make sure we are in an NMI call before we start doing anything.
      
      This was triggered by do_general_protection calling notify_die
      with DIE_GPF.
      Reported-by: NJan Kiszka <jan.kiszka@web.de>
      Signed-off-by: NDon Zickus <dzickus@redhat.com>
      LKML-Reference: <1294198689-15447-1-git-send-email-dzickus@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      9ab181fa
    • Y
      x86: Fix APIC ID sizing bug on larger systems, clean up MAX_APICS confusion · cb2ded37
      Yinghai Lu 提交于
      Found one x2apic pre-enabled system, x2apic_mode suddenly get
      corrupted after register some cpus, when compiled
      CONFIG_NR_CPUS=255 instead of 512.
      
      It turns out that generic_processor_info() ==> phyid_set(apicid,
      phys_cpu_present_map) causes the problem.
      
      phys_cpu_present_map is sized by MAX_APICS bits, and pre-enabled
      system some cpus have an apic id > 255.
      
      The variable after phys_cpu_present_map may get corrupted
      silently:
      
       ffffffff828e8420 B phys_cpu_present_map
       ffffffff828e8440 B apic_verbosity
       ffffffff828e8444 B local_apic_timer_c2_ok
       ffffffff828e8448 B disable_apic
       ffffffff828e844c B x2apic_mode
       ffffffff828e8450 B x2apic_disabled
       ffffffff828e8454 B num_processors
       ...
      
      Actually phys_cpu_present_map is referenced via apic id, instead
      index. We should use MAX_LOCAL_APIC instead MAX_APICS.
      
      For 64-bit it will be 32768 in all cases. BSS will increase by 4k bytes
      on 64-bit:
      
      	text		data		bss		dec		filename
      	21696943	4193748		12787712	38678403	vmlinux.before
      	21696943	4193748		12791808	38682499	vmlinux.after
      
      No change on 32bit.
      
      Finally we can remove MAX_APCIS that was rather confusing.
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: H. Peter Anvin <hpa@linux.intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      LKML-Reference: <4D23BD9C.3070102@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cb2ded37
    • R
      sh: correct definitions to access stack pointers · eac676e5
      Roel Kluin 提交于
      A definition like:
      
      #define regs_return_value(regs)	((regs)->regs[0])
      
      called with regs_return_value(foo) will be preprocessed to:
      
      ((foo)->foo[0])
              ^^^
      So to fix this to ensure the preprocessor compiles such calls correctly.
      Signed-off-by: NRoel Kluin <roel.kluin@gmail.com>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      eac676e5
  3. 04 1月, 2011 5 次提交
  4. 03 1月, 2011 5 次提交
    • A
      ARM: pxa: fix page table corruption on resume · 24c78557
      Aric D. Blumer 提交于
      Before this patch, the following error would sometimes occur after a
      resume on pxa3xx:
      
          /path/to/mm/memory.c:144: bad pmd 8040542e.
      
      The problem was that a temporary page table mapping was being improperly
      restored.
      
      The PXA3xx resume code creates a temporary mapping of resume_turn_on_mmu
      to avoid a prefetch abort.  The pxa3xx_resume_after_mmu code requires
      that the r1 register holding the address of this mapping not be
      modified, however, resume_turn_on_mmu does modify it. It is mostly
      correct in that r1 receives the base table address, but it may also
      get other bits in 13:0.  This results in pxa3xx_resume_after_mmu
      restoring the original mapping to the wrong place, corrupting memory
      and leaving the temporary mapping in place.
      Signed-off-by: NMatt Reimer <mreimer@sdgsystems.com>
      Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
      24c78557
    • M
      ARM: it8152: add IT8152_LAST_IRQ definition to fix build error · 823a2df2
      Mike Rapoport 提交于
      The commit 6ac6b817 (ARM: pxa: encode
      IRQ number into .nr_irqs) removed definition of ITE_LAST_IRQ which
      caused the following build error:
      
      CC      arch/arm/common/it8152.o
      arch/arm/common/it8152.c: In function 'it8152_init_irq':
      arch/arm/common/it8152.c:86: error: 'IT8152_LAST_IRQ' undeclared (first use in this function)
      arch/arm/common/it8152.c:86: error: (Each undeclared identifier is reported only once
      arch/arm/common/it8152.c:86: error: for each function it appears in.)
      make[2]: *** [arch/arm/common/it8152.o] Error 1
      
      Defining the IT8152_LAST_IRQ in the arch/arm/include/hardware/it8152.c
      fixes the build.
      Signed-off-by: NMike Rapoport <mike@compulab.co.il>
      Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
      823a2df2
    • L
      ARM: pxa: PXA_ESERIES depends on FB_W100. · 82427de2
      Lennert Buytenhek 提交于
      As arch/arm/mach-pxa/eseries.c references w100fb_gpio_{read,write}()
      directly.
      Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
      Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
      82427de2
    • R
      arch/x86/oprofile/op_model_amd.c: Perform initialisation on a single CPU · c7c25802
      Robert Richter 提交于
      Disable preemption in init_ibs(). The function only checks the
      ibs capabilities and sets up pci devices (if necessary). It runs
      only on one cpu but operates with the local APIC and some MSRs,
      thus it is better to disable preemption.
      
      [    7.034377] BUG: using smp_processor_id() in preemptible [00000000] code: modprobe/483
      [    7.034385] caller is setup_APIC_eilvt+0x155/0x180
      [    7.034389] Pid: 483, comm: modprobe Not tainted 2.6.37-rc1-20101110+ #1
      [    7.034392] Call Trace:
      [    7.034400]  [<ffffffff812a2b72>] debug_smp_processor_id+0xd2/0xf0
      [    7.034404]  [<ffffffff8101e985>] setup_APIC_eilvt+0x155/0x180
      [ ... ]
      
      Addresses https://bugzilla.kernel.org/show_bug.cgi?id=22812
      
      Reported-by: <atswartz@gmail.com>
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      Cc: oprofile-list@lists.sourceforge.net <oprofile-list@lists.sourceforge.net>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Rafael J. Wysocki <rjw@sisk.pl>
      Cc: Dan Carpenter <error27@gmail.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: <stable@kernel.org>         [2.6.37.x]
      LKML-Reference: <20110103111514.GM4739@erda.amd.com>
      [ small cleanups ]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c7c25802
    • A
      ARM: 6605/1: Add missing include "asm/memory.h" · 7c0ab43e
      Axel Lin 提交于
      This patch fixes below build error by adding the missing asm/memory.h,
      which is needed for arch_is_coherent().
      
      $ make pxa3xx_defconfig; make
        CC      init/do_mounts_rd.o
      In file included from include/linux/list_bl.h:5,
                       from include/linux/rculist_bl.h:7,
                       from include/linux/dcache.h:7,
                       from include/linux/fs.h:381,
                       from init/do_mounts_rd.c:3:
      include/linux/bit_spinlock.h: In function 'bit_spin_unlock':
      include/linux/bit_spinlock.h:61: error: implicit declaration of function 'arch_is_coherent'
      make[1]: *** [init/do_mounts_rd.o] Error 1
      make: *** [init] Error 2
      Signed-off-by: NAxel Lin <axel.lin@gmail.com>
      Acked-by: NPeter Huewe <peterhuewe@gmx.de>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      7c0ab43e
  5. 02 1月, 2011 1 次提交
  6. 29 12月, 2010 2 次提交
  7. 28 12月, 2010 1 次提交
    • C
      x86, paravirt: Use native_halt on a halt, not native_safe_halt · c8217b83
      Cliff Wickman 提交于
      halt() should use native_halt()
      safe_halt() uses native_safe_halt()
      
      If CONFIG_PARAVIRT=y, halt() is defined in arch/x86/include/asm/paravirt.h as
      
      static inline void halt(void)
      {
              PVOP_VCALL0(pv_irq_ops.safe_halt);
      }
      
      Otherwise (no CONFIG_PARAVIRT) halt() in arch/x86/include/asm/irqflags.h is
      
      static inline void halt(void)
      {
              native_halt();
      }
      
      So it looks to me like the CONFIG_PARAVIRT case of using native_safe_halt()
      for a halt() is an oversight.
      Am I missing something?
      
      It probably hasn't shown up as a problem because the local apic is disabled
      on a shutdown or restart.  But if we disable interrupts and call halt()
      we shouldn't expect that the halt() will re-enable interrupts.
      Signed-off-by: NCliff Wickman <cpw@sgi.com>
      LKML-Reference: <E1PSBcz-0001g1-FM@eag09.americas.sgi.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      c8217b83
  8. 27 12月, 2010 1 次提交
    • J
      x86/microcode: Fix double vfree() and remove redundant pointer checks before vfree() · 5cdd2de0
      Jesper Juhl 提交于
      In arch/x86/kernel/microcode_intel.c::generic_load_microcode()
      we have  this:
      
      	while (leftover) {
      		...
      		if (get_ucode_data(mc, ucode_ptr, mc_size) ||
      		    microcode_sanity_check(mc) < 0) {
      			vfree(mc);
      			break;
      		}
      		...
      	}
      
      	if (mc)
      		vfree(mc);
      
      This will cause a double free of 'mc'. This patch fixes that by
      just  removing the vfree() call in the loop since 'mc' will be
      freed nicely just  after we break out of the loop.
      
      There's also a second change in the patch. I noticed a lot of
      checks for  pointers being NULL before passing them to vfree().
      That's completely  redundant since vfree() deals gracefully with
      being passed a NULL pointer.  Removing the redundant checks
      yields a nice size decrease for the object  file.
      
      Size before the patch:
         text    data     bss     dec     hex filename
         4578     240    1032    5850    16da arch/x86/kernel/microcode_intel.o
      Size after the patch:
         text    data     bss     dec     hex filename
         4489     240     984    5713    1651 arch/x86/kernel/microcode_intel.o
      Signed-off-by: NJesper Juhl <jj@chaosbits.net>
      Acked-by: NTigran Aivazian <tigran@aivazian.fsnet.co.uk>
      Cc: Shaohua Li <shaohua.li@intel.com>
      LKML-Reference: <alpine.LNX.2.00.1012251946100.10759@swampdragon.chaosbits.net>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      5cdd2de0
  9. 24 12月, 2010 9 次提交
    • P
      sh: Tidy up SH-4A unaligned load support. · 1dee92bb
      Paul Mundt 提交于
      The current implementation was rather tied to the packed_struct.h
      definitions, which immediately began to clash when the packed_struct.h
      types changed and drivers began to include packed_struct.h directly.
      
      In order to support this sort of use it's necessary to get out of the way
      with regards to namespace collisions, and at the same time we can also
      kill off some duplicate code now that the unaligned headers are a bit
      more broken out.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      1dee92bb
    • T
      ARM: 6540/1: Stop irqsoff trace on return to user · d13e5edd
      Todd Android Poynor 提交于
      If the irqsoff tracer is in use, stop tracing the interrupt disable
      interval when returning to userspace.  Tracing userspace execution time
      as interrupts disabled time is not helpful for kernel performance
      analysis purposes.  Only do so if the irqsoff tracer is enabled, to
      avoid overhead for lockdep, which doesn't care.
      Signed-off-by: NTodd Poynor <toddpoynor@google.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      d13e5edd
    • S
      ARM: 6536/1: Add missing SZ_{32,64,128} · 537de3a6
      Stephen Warren 提交于
      ... and also remove misleading comment stating that this header is
      auto-generated.
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      Acked-by: NUwe Kleine-Knig <u.kleine-koenig@pengutronix.de>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      537de3a6
    • P
      sh: Fix up SH7201 clkfwk build. · 27f1accc
      Paul Mundt 提交于
      The master clock initialization for SH7201 was wholly bogus. Users of the
      legacy API must initialize the clock rate through the struct clk itself
      rather than returning the clock frequency. Given that the init function
      itself is void, returning the frequency isn't terribly effective.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      27f1accc
    • P
      sh: mach-se: Fix up SE7206 build. · 27434f0a
      Paul Mundt 提交于
      With some recent tidying of duplicate register definitions the se7206 IRQ
      code broke:
      
      arch/sh/boards/mach-se/7206/irq.c: error: 'INTC_ICR' undeclared (first use in this function)
      arch/sh/boards/mach-se/7206/irq.c: error: (Each undeclared identifier is reported only once
      arch/sh/boards/mach-se/7206/irq.c: error: for each function it appears in.)
      
      Fix it up.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      27434f0a
    • P
      sh: Fix up SH4-202 clkfwk build. · 638fa4aa
      Paul Mundt 提交于
      Some of the SH4-202 code was overlooked in the set_rate() API conversion,
      resulting in:
      
      arch/sh/kernel/cpu/sh4/clock-sh4-202.c: error: too many arguments to function 'clk->ops->set_rate'
      
      Fix it up.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      638fa4aa
    • Y
      x86, acpi: Parse all SRAT cpu entries even above the cpu number limitation · d3bd0588
      Yinghai Lu 提交于
      Recent Intel new system have different order in MADT, aka will list all thread0
      at first, then all thread1.
      But SRAT table still old order, it will list cpus in one socket all together.
      
      If the user have compiled limited NR_CPUS or boot with nr_cpus=, could have missed
      to put some cpus apic id to node mapping into apicid_to_node[].
      
      for example for 4 sockets system with 64 cpus with nr_cpus=32 will get crash...
      
      [    9.106288] Total of 32 processors activated (136190.88 BogoMIPS).
      [    9.235021] divide error: 0000 [#1] SMP
      [    9.235315] last sysfs file:
      [    9.235481] CPU 1
      [    9.235592] Modules linked in:
      [    9.245398]
      [    9.245478] Pid: 2, comm: kthreadd Not tainted 2.6.37-rc1-tip-yh-01782-ge92ef79-dirty #274      /Sun Fire x4800
      [    9.265415] RIP: 0010:[<ffffffff81075a8f>]  [<ffffffff81075a8f>] select_task_rq_fair+0x4f0/0x623
      ...
      [    9.645938] RIP  [<ffffffff81075a8f>] select_task_rq_fair+0x4f0/0x623
      [    9.665356]  RSP <ffff88103f8d1c40>
      [    9.665568] ---[ end trace 2296156d35fdfc87 ]---
      
      So let just parse all cpu entries in SRAT.
      
      Also add apicid checking with MAX_LOCAL_APIC, in case We could out of boundaries of
      apicid_to_node[].
      
      it fixes following bug too.
      https://bugzilla.kernel.org/show_bug.cgi?id=22662
      
      -v2: expand to 32bit according to hpa
         need to add MAX_LOCAL_APIC for 32bit
      Reported-and-Tested-by: NWu Fengguang <fengguang.wu@intel.com>
      Reported-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Tested-by: NMyron Stowe <myron.stowe@hp.com>
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      LKML-Reference: <4D0AD486.9020704@kernel.org>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      d3bd0588
    • Y
      x86, acpi: Add MAX_LOCAL_APIC for 32bit · 56d91f13
      Yinghai Lu 提交于
      We should use MAX_LOCAL_APIC for max apic ids and MAX_APICS as number
      of local apics.
      
      Also apic_version[] array should use MAX_LOCAL_APICs.
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      LKML-Reference: <4D0AD464.2020408@kernel.org>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      56d91f13
    • W
      powerpc/mpc5200: include fs.h in mpc52xx_gpt.c · 5e2f55c6
      Wolfram Sang 提交于
      Fix build errors like these (from a randconfig and my defconfig for a custom board):
      
      src/arch/powerpc/platforms/52xx/mpc52xx_gpt.c:549: error: dereferencing pointer to incomplete type: 1 errors in 1 logs
      src/arch/powerpc/platforms/52xx/mpc52xx_gpt.c:636: error: implicit declaration of function 'nonseekable_open': 1 errors in 1 logs
      src/arch/powerpc/platforms/52xx/mpc52xx_gpt.c:657: error: variable 'mpc52xx_wdt_fops' has initializer but incomplete type: 1 errors in 1 logs
      src/arch/powerpc/platforms/52xx/mpc52xx_gpt.c:658: error: excess elements in struct initializer: 1 errors in 1 logs
      src/arch/powerpc/platforms/52xx/mpc52xx_gpt.c:658: error: unknown field 'owner' specified in initializer: 1 errors in 1 logs
      ...
      Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org>
      Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      5e2f55c6
  10. 23 12月, 2010 1 次提交
    • D
      x86, nmi_watchdog: Remove ARCH_HAS_NMI_WATCHDOG and rely on CONFIG_HARDLOCKUP_DETECTOR · 4a7863cc
      Don Zickus 提交于
      The x86 arch has shifted its use of the nmi_watchdog from a
      local implementation to the global one provide by
      kernel/watchdog.c.  This shift has caused a whole bunch of
      compile problems under different config options.  I attempt to
      simplify things with the patch below.
      
      In order to simplify things, I had to come to terms with the
      meaning of two terms ARCH_HAS_NMI_WATCHDOG and
      CONFIG_HARDLOCKUP_DETECTOR.  Basically they mean the same thing,
      the former on a local level and the latter on a global level.
      
      With the old x86 nmi watchdog gone, there is no need to rely on
      defining the ARCH_HAS_NMI_WATCHDOG variable because it doesn't
      make sense any more.  x86 will now use the global
      implementation.
      
      The changes below do a few things.  First it changes the few
      places that relied on ARCH_HAS_NMI_WATCHDOG to use
      CONFIG_X86_LOCAL_APIC (the former was an alias for the latter
      anyway, so nothing unusual here).  Those pieces of code were
      relying more on local apic functionality the nmi watchdog
      functionality, so the change should make sense.
      
      Second, I removed the x86 implementation of
      touch_nmi_watchdog().  It isn't need now, instead x86 will rely
      on kernel/watchdog.c's implementation.
      
      Third, I removed the #define ARCH_HAS_NMI_WATCHDOG itself from
      x86.  And tweaked the include/linux/nmi.h file to tell users to
      look for an externally defined touch_nmi_watchdog in the case of
      ARCH_HAS_NMI_WATCHDOG _or_ CONFIG_HARDLOCKUP_DETECTOR. This
      changes removes some of the ugliness in that file.
      
      Finally, I added a Kconfig dependency for
      CONFIG_HARDLOCKUP_DETECTOR that said you can't have
      ARCH_HAS_NMI_WATCHDOG _and_ CONFIG_HARDLOCKUP_DETECTOR.  You can
      only have one nmi_watchdog.
      
      Tested with
      ARCH=i386: allnoconfig, defconfig, allyesconfig, (various broken
      configs) ARCH=x86_64: allnoconfig, defconfig, allyesconfig,
      (various broken configs)
      
      Hopefully, after this patch I won't get any more compile broken
      emails. :-)
      
      v3:
        changed a couple of 'linux/nmi.h' -> 'asm/nmi.h' to pick-up correct function
        prototypes when CONFIG_HARDLOCKUP_DETECTOR is not set.
      Signed-off-by: NDon Zickus <dzickus@redhat.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: fweisbec@gmail.com
      LKML-Reference: <1293044403-14117-1-git-send-email-dzickus@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4a7863cc
  11. 22 12月, 2010 3 次提交
  12. 21 12月, 2010 1 次提交
  13. 20 12月, 2010 3 次提交
    • N
      ARM: fix cache-feroceon-l2 after stack based kmap_atomic() · 6d3e6d36
      Nicolas Pitre 提交于
      Since commit 3e4d3af5 "mm: stack based kmap_atomic()", it is actively
      wrong to rely on fixed kmap type indices (namely KM_L2_CACHE) as
      kmap_atomic() totally ignores them and a concurrent instance of it may
      happily reuse any slot for any purpose.  Because kmap_atomic() is now
      able to deal with reentrancy, we can get rid of the ad hoc mapping here.
      
      While the code is made much simpler, there is a needless cache flush
      introduced by the usage of __kunmap_atomic().  It is not clear if the
      performance difference to remove that is worth the cost in code
      maintenance (I don't think there are that many highmem users on that
      platform anyway) but that should be reconsidered when/if someone cares
      enough to do some measurements.
      Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      6d3e6d36
    • N
      ARM: fix cache-xsc3l2 after stack based kmap_atomic() · 25cbe454
      Nicolas Pitre 提交于
      Since commit 3e4d3af5 "mm: stack based kmap_atomic()", it is actively
      wrong to rely on fixed kmap type indices (namely KM_L2_CACHE) as
      kmap_atomic() totally ignores them and a concurrent instance of it may
      happily reuse any slot for any purpose.  Because kmap_atomic() is now
      able to deal with reentrancy, we can get rid of the ad hoc mapping here,
      and we even don't have to disable IRQs anymore (highmem case).
      
      While the code is made much simpler, there is a needless cache flush
      introduced by the usage of __kunmap_atomic().  It is not clear if the
      performance difference to remove that is worth the cost in code
      maintenance (I don't think there are that many highmem users on that
      platform if at all anyway).
      Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      25cbe454
    • N
      ARM: get rid of kmap_high_l1_vipt() · 39af22a7
      Nicolas Pitre 提交于
      Since commit 3e4d3af5 "mm: stack based kmap_atomic()", it is no longer
      necessary to carry an ad hoc version of kmap_atomic() added in commit
      7e5a69e8 "ARM: 6007/1: fix highmem with VIPT cache and DMA" to cope
      with reentrancy.
      
      In fact, it is now actively wrong to rely on fixed kmap type indices
      (namely KM_L1_CACHE) as kmap_atomic() totally ignores them now and a
      concurrent instance of it may reuse any slot for any purpose.
      Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      39af22a7
  14. 19 12月, 2010 2 次提交