1. 19 12月, 2016 1 次提交
  2. 15 12月, 2016 2 次提交
    • V
      ARCv2: intc: default all interrupts to priority 1 · 107177b1
      Vineet Gupta 提交于
      ARC HS Cores support configurable multiple interrupt priorities of upto
      16 levels. In commit dec2b284 ("ARCv2: intc: Allow interruption by
      lowest priority interrupt") we switched to 15 which seems a bit
      excessive given that there would be rare hardware implementing so many
      preemption levels AND running Linux. It would seem that 2 levels will be
      more common so switch to 1 as the default priority level. This will be
      the "lower" priority level saving 0 for implementing NMI style support.
      
      This scheme also works in systems with more than 2 prioity levels as
      well.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      107177b1
    • V
      ARCv2: entry: document intr disable in hard isr · 78833e79
      Vineet Gupta 提交于
      And while at it - use the proper assembler macro which includes the
      optional irq tracing already - de-uglify'ing the code a bit
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      78833e79
  3. 14 12月, 2016 1 次提交
  4. 01 12月, 2016 14 次提交
  5. 30 11月, 2016 1 次提交
  6. 29 11月, 2016 2 次提交
  7. 28 11月, 2016 3 次提交
  8. 27 11月, 2016 8 次提交
  9. 26 11月, 2016 8 次提交