Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.

The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

It should be SOCFPGA instead of SOCFGPA.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

The clk_name field from the socfpga_clk struct is unused.
Remove it.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk.
Now that twd-timer's clock phandle is populated in the DTS, we can remove
this function.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

After the patch:
"clk: socfpga: Map the clk manager base address in the clock driver"

The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace
looking for the GPIO_DB_CLK by its divider offset instead.

Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as
this represents the GPIO_DB_CLK.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

The clk manager's base address was being mapped in SOCFPGA's arch code and
being extern'ed out to the clock driver. This method is not correct, and the
arch code was not really doing anything with that clk manager anyways.

This patch moves the mapping of the clk manager's base address in the clock
driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all
the clocks.
Suggested-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
---
v2: Use a static declaration for the clk_mgr_base_addr. Clean up the
    CLK_OF_DECLARE() as suggested by Arnd.

'div_reg' is a pointer. Assign NULL instead of 0.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this,
the SD driver was getting the incorrect clock value. This prevented the
SD driver from initializing correctly.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Reviewed-by: NPavel Machek <pavel@denx.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Acked-by: NMike Turquette <mturquette@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>

v4:
- Add Acked-by: Mike Turquette

v3:
- Addressed comments from Pavel

v2:
- Fix space/indent errors
- Add streq for strcmp == 0
Signed-off-by: NOlof Johansson <olof@lixom.net>

With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>