This change is to support MESA performace optimization.
Modify CS IOCTL to allow its input as command buffer and an array of
buffer handles to create a temporay bo list and then destroy it
when IOCTL completes.
This saves on calling for BO_LIST create and destry IOCTLs in MESA
and by this improves performance.

v2: Avoid inserting the temp list into idr struct.

v3:
Remove idr alloation from amdgpu_bo_list_create.
Remove useless argument from amdgpu_cs_parser_fini
Minor cosmetic stuff.

v4: Revert amdgpu_bo_list_destroy back to static
Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NChunming Zhou <david1.zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit b87079ec.

SMU FW team ask to remove this version specific code.
Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

return a uint32_t rather than an int to properly reflect
what the function does.
Reviewed-by: NRex Zhu <rezhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Split out the shared smumgr code for vega10 and 12
so we don't have duplicate code for both.
Reviewed-by: NRex Zhu <rezhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Commented out.
Reviewed-by: NRex Zhu <rezhu@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Rather than calculating it everytime we rebuild the toc
buffer, calculate it once initially and then just copy
the cached results to the vram buffer.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

use the structure member directly.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

use kaddr directly rather than secondary variable.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Rather than using the index variable stored in vram.  If
the device fails to come back online after a resume cycle,
reads from vram will return all 1s which will cause a
segfault. Based on a patch from Thomas Martitz <kugel@rockbox.org>.
This avoids the segfault, but we still need to sort out
why the GPU does not come back online after a resume.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105760Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use the PP_STATE_SUPPORT_* rather than AMD_CG_SUPPORT_*
when communicating with the SMU.
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Currently we do not turn off autocal when scaling is in bypass.
In case vbios enalbes auto scale and our first mode set is a non-scaled
mode we have autocal on causing screen corruption.

[how]
moves turning autocal off to be first thing done during scaler setup
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why] Prevent unexpected color shows if DalMpVisualConfirm enable.
[How] Zero out color configuration data for DalMpVisualConfirm when initiating.
Signed-off-by: NHugo Hu <hugo.hu@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DV updated their dml with an option to use max vstartup,
this updates dc dml with the same option
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The previous code could allow through attempts to enable more streams
than there are timing generators, in designs where the number of pipes
is greater than the number of timing generators.

[How]
Compare the new stream count to the resource pool's timing generator
count, instead of its pipe count.  Also correct a typo in the error
message.
Signed-off-by: NKen Chalmers <ken.chalmers@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
when hw team does phy parameters tuning, there is need to force dp
link rate or lane count grater than the values from dp receiver to
check dp tx. current debufs limit link rate, lane count no more
than rx caps.

[How] remove force settings less than rx caps check

v2: Fix typo in title
Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDavid Francis <David.Francis@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Regamma/CTM tests require CRC support

[How]
The CRC registers that were used in DCE exist under different
names in DCN.  The code was copied from DCE (in
dc/dce110/dce110_timing_generator.c) into DCN, and changed to
use the DCN register access helper functions.
Signed-off-by: NDavid Francis <David.Francis@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NFatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
PNP cause bsod regression fix

[HOW]
Add NULL check
Signed-off-by: NYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: NHugo Hu <Hugo.Hu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Add a switch statement to translate pp's powerlevel enum
to dc powerlevel statement enum
[how]
Add a translator function
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
"DalEnableHDMI20" set to 0, disallow HDMI YCbCr420 and  pixel clock > 340Mhz
Default is enabled.
Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
get_channel_status() can return 0 in returned_bytes, and report a
successful operation result. This is because it prunes the first status
byte out. This was preventing read_channel_reply() from being called
(due to the faulty condition), and consequently preventing the AUX
reply status from being set.

[How]
Fix the conditional so that it accounts for when get_channel_status()
returns 0 bytes read.

[Fixes]
Fixes possible edid read failures during S3 resume, where we are now
relying on DRM's DP AUX handling. This was an regression introduced by:

    Author: Harry Wentland <harry.wentland@amd.com>
        drm/amd/display: Return aux replies directly to DRM
Signed-off-by: NLeo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
There is no point in keeping the AUX reply value in the raw format as
returned from reading the AUX_SW_DATA register.

[How]
Shift it within read_channel_reply(), where the register is read, before
returning it.
Signed-off-by: NLeo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: Remove spurious newline changes
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some monitors mark 4K@60 capable HDMI port only have 300MHz TMDS
maximum, but the edid includes 4K@60 mode in cea extension block.

[How]
To enable 4K@60, need to limit BW by allowing YCbCr420 ONLY mode.
Add YCbCr420 only support for monitors that do not fully support
HDMI2.0, e.g., ASUS PA328. The YCbCr420 only support applies to
DCN, DCE112 or higher.
Signed-off-by: NJerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

bug fix: phy test PLTAT is special 80bit test pattern. The 80bit
data should be hard coded within driver so that user does not
need input the deata. previous driver does not have hard coded
80 bits pattern data for PLTPAT. Other than this PLTPAT, user
has to input 80 bits pattern data. In case user input less than
10 bytes data, un-input data byte will be filled by 0x00.
Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: NDuke Du <Duke.Du@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

GCC 4.9 reports a 'missing braces around initializer' error. This is a
bug, documented here:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119

Fix it by adding another brace.
Signed-off-by: NLeo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: NMikita Lipski <Mikita.Lipski@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

 function: get current DP PHY settings: voltage swing, pre-emphasis,
 post-cursor2 (defined by VESA DP specification)

 valid values:  voltage swing: 0,1,2,3  pre-emphasis : 0,1,2,3
 post cursor2 : 0,1,2,3

 debugfs file phy_setings is located at  /sys/kernel/debug/dri/0/DP-x

 there will be directories, like DP-1, DP-2,DP-3, etc. for DP display

 --- to figure out which DP-x is the display for DP to be check,
 cd DP-x
 ls -ll
 There should be debugfs file, like link_settings, phy_settings.
 cat link_settings
 from lane_count, link_rate to figure which DP-x is for display to be
 worked on

 --- to get current DP PHY settings,
 cat phy_settings

 --- to change DP PHY settings,
 echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings

 for examle, to change voltage swing to 2, pre-emphasis to 3,
 post_cursor2 to 0,
 echo 2 3 0 > phy_settings

 ---  to check if change be applied, get current phy settings by
 cat phy_settings

 ---  in case invalid values are set by user, like
 echo 1 4 0 > phy_settings

 HW will NOT be programmed by these settings.

cat phy_settings will show the previous valid settings.
Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NHersen Wu <hersenxs.wu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
In eDP spec, the min duration in LCDVDD on-off-on sequence should be
500ms, some BOE panels need 700ms to pass.
[HOW]
Add patch to wait more time when eDP power on.
Signed-off-by: NHugo Hu <hugo.hu@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>