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  1. 14 1月, 2015 7 次提交
  3. 16 12月, 2014 2 次提交
  5. 14 12月, 2014 1 次提交
  7. 12 12月, 2014 1 次提交
  9. 11 12月, 2014 6 次提交
  11. 09 12月, 2014 1 次提交
  13. 08 12月, 2014 3 次提交
  15. 06 12月, 2014 1 次提交
  17. 05 12月, 2014 1 次提交
    • D
      clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers · 65b5732d
      由 Doug Anderson 提交于 
      Some 32-bit (ARMv7) systems are architected like this:

* The firmware doesn't know and doesn't care about hypervisor mode and
  we don't want to add the complexity of hypervisor there.

* The firmware isn't involved in SMP bringup or resume.

* The ARCH timer come up with an uninitialized offset (CNTVOFF)
  between the virtual and physical counters.  Each core gets a
  different random offset.

* The device boots in "Secure SVC" mode.

* Nothing has touched the reset value of CNTHCTL.PL1PCEN or
  CNTHCTL.PL1PCTEN (both default to 1 at reset)

On systems like the above, it doesn't make sense to use the virtual
counter.  There's nobody managing the offset and each time a core goes
down and comes back up it will get reinitialized to some other random
value.

This adds an optional property which can inform the kernel of this
situation, and firmware is free to remove the property if it is going
to initialize the CNTVOFF registers when each CPU comes out of reset.

Currently, the best course of action in this case is to use the
physical timer, which is why it is important that CNTHCTL hasn't been
changed from its reset value and it's a reasonable assumption given
that the firmware has never entered HYP mode.

Note that it's been said that on ARMv8 systems the firmware and
kernel really can't be architected as described above.  That means
using the physical timer like this really only makes sense for ARMv7
systems.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NSonny Rao <sonnyrao@chromium.org>
Reviewed-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      65b5732d
  19. 04 12月, 2014 2 次提交
  21. 03 12月, 2014 3 次提交
  23. 02 12月, 2014 5 次提交
  25. 01 12月, 2014 4 次提交
  27. 29 11月, 2014 1 次提交
  29. 28 11月, 2014 1 次提交
    • L
      ARM: dt: fix up PL011 device tree bindings · a81a6c65
      由 Linus Walleij 提交于 
      Make the map match the reality, the current binding text is
nonsense:

- The clock required for the clocking of the serial port
  must come first and is not optional (as the driver will
  otherwise proceed to grab and use the apb_pclk as uartclk),
  and the apb_pclk that clocks the logic must come second
  as the code will retrieve the first clock by index,
  whereas the PrimeCell but will explicitly look for
  "apb_pclk" so this can be specified later, as it is
  looked up by name.

- The pin control state "default" is the only mandated
  state, the sleep state is entirely optional.

We also add an example to avoid further confusion.
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGrant Likely <grant.likely@linaro.org>
      a81a6c65
  31. 27 11月, 2014 1 次提交