1. 17 9月, 2011 1 次提交
    • I
      ARM: davinci: Explicitly set channel controllers' default queues · f23fe857
      Ido Yariv 提交于
      Davinci platforms may define a default queue for each channel
      controller. If one is not defined, the default queue is set to EVENTQ_1.
      However, there's no way to distinguish between an unset default queue to
      one that is set to EVENTQ_0, as EVENTQ_0 = 0.
      
      Explicitly specify the default queue for all channel controllers on all
      Davinci platforms to EVENTQ_1, and don't overwrite it in the EDMA probe
      function.
      
      One exception is the DA850 board, for which EVENTQ_1 is not a valid
      option for its second channel controller. Use EVENTQ_0 instead for that
      channel controller.
      Signed-off-by: NIdo Yariv <ido@wizery.com>
      Signed-off-by: NSekhar Nori <nsekhar@ti.com>
      f23fe857
  2. 15 3月, 2011 1 次提交
  3. 10 12月, 2010 1 次提交
  4. 24 9月, 2010 2 次提交
  5. 06 8月, 2010 1 次提交
  6. 22 6月, 2010 1 次提交
    • C
      Davinci: tnetv107x soc support · 4d1e7848
      Cyril Chemparathy 提交于
      TNETV107X is a Texas Instruments SOC that shares a number of common features
      with the Davinci architecture.  Some of the key differences between
      traditional Davincis and this new SOC are as follow:
      
      1. The SOCs clock architecture includes a new spread-spectrum PLL.  Some
      elements of the clock architecture are reused from Davinci (e.g. LPSC), but
      the PLL related code is overridden using existing interfaces in "struct clk".
      
      2. The MMR layout on this SOC is substantially different from Davinci.
      Consequently, the fixed I/O map is a whole lot more convoluted (more so than
      DA8xx).  The net impact here is that IO_ADDRESS() will not work on this SoC,
      and therefore all mappings have to be through ioremap().
      Signed-off-by: NCyril Chemparathy <cyril@ti.com>
      Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      4d1e7848