- 22 2月, 2017 1 次提交
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由 Kishon Vijay Abraham I 提交于
Group all the PCI drivers that use DesignWare core in dwc directory. dwc IP is capable of operating in both host mode and device mode and keeping it inside the *host* directory is misleading. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jingoohan1@gmail.com> Acked-By: NJoao Pinto <jpinto@synopsys.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Minghuan Lian <minghuan.Lian@freescale.com> Cc: Mingkai Hu <mingkai.hu@freescale.com> Cc: Roy Zang <tie-fei.zang@freescale.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
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- 11 10月, 2016 3 次提交
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由 Bjorn Helgaas 提交于
Export dw_pcie_readl_rc() and dw_pcie_writel_rc(). Many other drivers can use these instead of implementing their own versions. No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers allow a driver to override the default DesignWare register accessors. Make the signature of the override functions the same as the default accessors. This makes the default dw_pcie_readl_rc() and the corresponding override more structurally similar: both will compute the final register address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed the address and passed it to the override. No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 23 8月, 2016 1 次提交
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由 Pratyush Anand 提交于
Most of the platforms have 3 or more viewports. For such platforms, We do not need to share viewports between IO and CFG. Assign viewport 2 to IO transactions in such cases. Tested-by: NDong Bo <dongbo4@huawei.com> Signed-off-by: NPratyush Anand <pratyush.anand@gmail.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRob Herring <robh@kernel.org>
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- 18 8月, 2016 3 次提交
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由 Joao Pinto 提交于
Add support for the new iATU Unroll mechanism that will be used from Core version 4.80. The new Cores can support either iATU Unroll or the "old" iATU method, now called Legacy Mode. The driver is perfectly capable of performing well for both. [bhelgaas: split ATU enable timeout to separate patch] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Joao Pinto 提交于
Move the link wait sleep definitions to the .c file as suggested by Jisheng Zhang in a previous patch. Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Jisheng Zhang <jszhang@marvell.com>
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由 Bjorn Helgaas 提交于
dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in space supplied by the caller. Return the u32 value directly instead. This makes the calling code read better and makes it obvious that the caller need not initialize the storage. In the following example it isn't clear whether "val" is initialized before being used: dw_pcie_readl_rc(pp, PCI_COMMAND, &val); if (val & PCI_COMMAND_MEMORY) ... No functional change intended. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 15 3月, 2016 1 次提交
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由 Joao Pinto 提交于
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and spear13xx) had similar loops waiting for the link to come up. Add a generic dw_pcie_wait_for_link() for use by all these drivers so the waiting is done consistently, e.g., always using usleep_range() rather than mdelay() and using similar timeouts and retry counts. Note that this changes the Keystone link training/wait for link strategy, so we initiate link training, then wait longer for the link to come up before re-initiating link training. [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] Signed-off-by: NJoao Pinto <jpinto@synopsys.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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- 03 11月, 2015 4 次提交
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由 Zhou Wang 提交于
Previously, dw_pcie_host_init() created the PCI host bridge with pci_common_init_dev(), an ARM-specific function that supplies the ARM- specific pci_sys_data structure as the PCI "sysdata". Make pcie-designware.c arch-agnostic by reimplementing the functionality of pci_common_init_dev() directly in dw_pcie_host_init(). Note that this changes the bridge sysdata from the ARM pci_sys_data to the DesignWare pcie_port structure. This doesn't affect the ARM sysdata users because they are all specific to non-DesignWare host bridges, which will still have pci_sys_data. [bhelgaas: changelog] Tested-by: NJames Morse <james.morse@arm.com> Tested-by: NGabriel Fernandez <gabriel.fernandez@st.com> Tested-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com> Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Zhou Wang 提交于
Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF DT parser. [bhelgaas: changelog] Tested-by: NJames Morse <james.morse@arm.com> Tested-by: NGabriel Fernandez <gabriel.fernandez@st.com> Tested-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com> Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Zhou Wang 提交于
Revert f4c55c5a ("PCI: designware: Program ATU with untranslated address"). Note that dra7xx_pcie_host_init() now modifies pp->io_base, but we still need the original value for dw_pcie_setup() in the path below, so this adds a new io_base_tmp member. It will be removed later when dw_pcie_setup() is removed. dra7xx_add_pcie_port dw_pcie_host_init pp->io_base = range.cpu_addr pp->io_base_tmp = range.cpu_addr # <-- added pp->ops->host_init dra7xx_pcie_host_init # ops->host_init pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR # <-- modified pci_common_init_dev(..., &dw_pci) pcibios_init_hw hw->setup dw_pcie_setup # hw_pci.setup pci_ioremap_io(..., pp->io_base_tmp) # <-- original addr required [bhelgaas: changelog] Tested-by: NJames Morse <james.morse@arm.com> Tested-by: NGabriel Fernandez <gabriel.fernandez@st.com> Tested-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com> Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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由 Gabriele Paoloni 提交于
Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to split the address into "addr" and "where". The callees assumed "addr" was 32-bit aligned (with zeros in the low two bits) and they used only the low two bits of "where". Accept the entire address in "addr" and drop the now-redundant "where" argument. As an example, this replaces this: int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) *val = readb(addr + (where & 1)); with this: int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) *val = readb(addr): [bhelgaas: changelog, split access size change to separate patch] Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 19 9月, 2015 1 次提交
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由 Lucas Stach 提交于
Make get_msi_addr() return phys_addr_t, not u32. This allows the MSI target address to be above 4GB for 64bit or PAE systems. No functional change for the current 32bit platform users as phys_addr_t maps to u32 for them. [bhelgaas: changelog] Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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- 12 11月, 2014 1 次提交
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由 Yijing Wang 提交于
"msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 24 9月, 2014 2 次提交
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由 Minghuan Lian 提交于
Add a struct pcie_host_ops .get_msi_data() method for platforms to return their special MSI message data. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com>
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由 Minghuan Lian 提交于
The struct pcie_host_ops .get_msi_data() method returns the MSI message address. To accurately express its purpose, rename it to .get_msi_addr(). Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com>
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- 06 9月, 2014 1 次提交
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由 Pratyush Anand 提交于
The struct pcie_port_info doesn't contain any exclusive information compared to other elements of struct pcie_port. So, keeping a separate structure does not seem very logical. Therefore remove this struct and embed its elements directly into struct pcie_port. Signed-off-by: NPratyush Anand <pratyush.anand@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit Kumar <mohit.kumar@st.com>
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- 05 9月, 2014 1 次提交
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由 Lucas Stach 提交于
This allows to explicitly specify the covered bus numbers in the devicetree, which will come in handy once we see a SoC with more than one PCIe host controller instance. Previously the driver relied on the behavior of pci_scan_root_bus() to fill in a range of 0x00-0xff if no valid range was found. We fall back to the same range if no valid DT entry was found to keep backwards compatibility, but now do it explicitly. [bhelgaas: use %pR in error message to avoid duplication] Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit Kumar <mohit.kumar@st.com>
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- 03 9月, 2014 1 次提交
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由 Murali Karicheri 提交于
The Keystone PCI controller is based on v3.65 DesignWare hardware. This version differs from newer versions of the hardware in functional areas discussed below that make it necessary to change dw_pcie_host_init() to support v3.65 based PCI controller. 1. No support for ATU port. Any ATU-specific resource handling code is to be bypassed for v3.65 h/w. 2. MSI controller uses application space to implement MSI and 32 MSI interrupts are multiplexed over 8 IRQs to the host. Hence the code to process MSI IRQ needs to be different. This patch allows platform driver to provide its own irq_domain_ops ptr to irq_domain_add_linear() through an API callback from the DesignWare core driver. 3. MSI interrupt generation requires EP to write to the RC's application register. So enhance the driver to allow setup of inbound access to MSI IRQ register as a post scan bus API callback. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com> CC: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Jingoo Han <jg1.han@samsung.com> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
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- 23 7月, 2014 3 次提交
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由 Murali Karicheri 提交于
DesignWare v3.65 hardware implements MSI controller registers in application space. This requires updates to the DesignWare core to support controllers based on this older hardware. Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit in the application register. Also, v3.65 hardware uses the MSI_IRQ register in application register space to raise MSI IRQ to the RC from EP. Current code uses the standard mechanism as per PCI spec. So add get_msi_data() to get the address of this register so common code can work on both v3.65 and newer hardware. [bhelgaas: changelog] Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit Kumar <mohit.kumar@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
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由 Murali Karicheri 提交于
DesignWare v3.65 hardware requires application space registers to be configured to access the remote EP config space. To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops. [bhelgaas: changelog] Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit Kumar <mohit.kumar@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
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由 Kishon Vijay Abraham I 提交于
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see only 28-bit addresses. So whenever the CPU issues a read/write request, the 4 most significant bits are used by L3 to determine the target controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff] for the PCIe controller but the PCIe controller will see only [0x00000000-0x0fffffff]. For programming the outbound translation window the *base* should be programmed as 0x00000000. Whenever we try to write to, e.g., 0x20000000, it will be translated to whatever we have programmed in the translation window with base as 0x00000000. This is needed when the dt node is modelled something like this: axi { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; ranges = <0x0 0x20000000 0x10000000 // 28-bit bus 0x51000000 0x51000000 0x3000>; pcie@51000000 { reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>; reg-names = "config", "ti_conf", "rc_dbics"; #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; }; }; Here the CPU address for configuration space is 0x20013000 and the controller address for configuration space is 0x13000. The controller address should be used while programming the ATU (in order for translation to happen properly in DRA7xx). Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMohit Kumar <mohit.kumar@st.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
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- 31 5月, 2014 1 次提交
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由 Lucas Stach 提交于
On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make sure we don't bail too early from the IRQ handler. The issue is fairly theoretical as it would require a system setup with a PCIe switch where one connected device is using legacy INTD and another one using MSI, but better fix it now. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NRichard Zhu <r65037@freescale.com>
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- 17 4月, 2014 1 次提交
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由 Andrew Murray 提交于
Serialization of configuration accesses is provided by 'pci_lock' in drivers/pci/access.c thus making the driver's 'conf_lock' superfluous. Signed-off-by: NAndrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NRichard Zhu <r65037@freescale.com>
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- 21 12月, 2013 1 次提交
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由 Pratyush Anand 提交于
The cfg_read/write functions are DesignWare-specific. Add dw_pcie prefix to avoid collision in global name space. Tested-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NPratyush Anand <pratyush.anand@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: NJingoo Han <jg1.han@samsung.com>
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- 09 10月, 2013 3 次提交
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由 Pratyush Anand 提交于
Without irq_create_mapping(), the correct IRQ number cannot be provided. In this case, it makes problems such as NULL dereference. Thus, irq_create_mapping() should be added for MSI. Suggested-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NPratyush Anand <pratyush.anand@st.com> Signed-off-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Bjorn Helgaas 提交于
The following variables and functions are used only in pcie-designware.c, so make them static: global_io_offset dw_pcie_rd_own_conf() dw_pcie_wr_own_conf() dw_pcie_setup() dw_pcie_scan_bus() dw_pcie_map_irq() Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com>
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由 Seungwon Jeon 提交于
Add header guards to prevent redundant inclusion. Signed-off-by: NSeungwon Jeon <tgih.jun@samsung.com> Signed-off-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 26 9月, 2013 1 次提交
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由 Jingoo Han 提交于
This patch adds support for Message Signaled Interrupt in the Exynos PCIe driver using Synopsys designware PCIe core IP. Signed-off-by: NSiva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: NSrikanth T Shivanand <ts.srikanth@samsung.com> Signed-off-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
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- 13 8月, 2013 1 次提交
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由 Jingoo Han 提交于
Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
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