1. 26 8月, 2021 2 次提交
  2. 17 6月, 2021 1 次提交
  3. 25 5月, 2021 2 次提交
  4. 13 5月, 2021 1 次提交
  5. 06 4月, 2021 1 次提交
  6. 23 3月, 2021 1 次提交
    • J
      USB: xhci: drop workaround for forced irq threading · 5e712172
      Johan Hovold 提交于
      Force-threaded interrupt handlers used to run with interrupts enabled,
      something which could lead to deadlocks in case a threaded handler
      shared a lock with code running in hard interrupt context (e.g. timer
      callbacks) and did not explicitly disable interrupts.
      
      Since commit 81e2073c ("genirq: Disable interrupts for force
      threaded handlers") interrupt handlers always run with interrupts
      disabled on non-RT so that drivers no longer need to do handle forced
      threading ("threadirqs").
      
      Drop the now obsolete workaround added by commit 63aea0db ("USB:
      xhci: fix lock-inversion problem").
      
      Cc: Alan Stern <stern@rowland.harvard.edu>
      Cc: Bart Van Assche <bart.vanassche@sandisk.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Signed-off-by: NJohan Hovold <johan@kernel.org>
      Link: https://lore.kernel.org/r/20210322111140.32056-1-johan@kernel.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5e712172
  7. 11 3月, 2021 1 次提交
  8. 10 3月, 2021 1 次提交
  9. 03 2月, 2021 1 次提交
  10. 29 1月, 2021 27 次提交
  11. 16 1月, 2021 1 次提交
    • M
      xhci: make sure TRB is fully written before giving it to the controller · 576667ba
      Mathias Nyman 提交于
      Once the command ring doorbell is rung the xHC controller will parse all
      command TRBs on the command ring that have the cycle bit set properly.
      
      If the driver just started writing the next command TRB to the ring when
      hardware finished the previous TRB, then HW might fetch an incomplete TRB
      as long as its cycle bit set correctly.
      
      A command TRB is 16 bytes (128 bits) long.
      Driver writes the command TRB in four 32 bit chunks, with the chunk
      containing the cycle bit last. This does however not guarantee that
      chunks actually get written in that order.
      
      This was detected in stress testing when canceling URBs with several
      connected USB devices.
      Two consecutive "Set TR Dequeue pointer" commands got queued right
      after each other, and the second one was only partially written when
      the controller parsed it, causing the dequeue pointer to be set
      to bogus values. This was seen as error messages:
      
      "Mismatch between completed Set TR Deq Ptr command & xHCI internal state"
      
      Solution is to add a write memory barrier before writing the cycle bit.
      
      Cc: <stable@vger.kernel.org>
      Tested-by: NRoss Zwisler <zwisler@google.com>
      Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
      Link: https://lore.kernel.org/r/20210115161907.2875631-2-mathias.nyman@linux.intel.comSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      576667ba
  12. 09 12月, 2020 1 次提交
    • T
      usb: xhci: Use temporary buffer to consolidate SG · 2017a1e5
      Tejas Joglekar 提交于
      The Synopsys xHC has an internal TRB cache of size TRB_CACHE_SIZE for
      each endpoint. The default value for TRB_CACHE_SIZE is 16 for SS and 8
      for HS. The controller loads and updates the TRB cache from the transfer
      ring in system memory whenever the driver issues a start transfer or
      update transfer command.
      
      For chained TRBs, the Synopsys xHC requires that the total amount of
      bytes for all TRBs loaded in the TRB cache be greater than or equal to 1
      MPS. Or the chain ends within the TRB cache (with a last TRB).
      
      If this requirement is not met, the controller will not be able to send
      or receive a packet and it will hang causing a driver timeout and error.
      
      This can be a problem if a class driver queues SG requests with many
      small-buffer entries. The XHCI driver will create a chained TRB for each
      entry which may trigger this issue.
      
      This patch adds logic to the XHCI driver to detect and prevent this from
      happening.
      
      For every (TRB_CACHE_SIZE - 2), we check the total buffer size of
      the SG list and if the last window of (TRB_CACHE_SIZE - 2) SG list length
      and we don't make up at least 1 MPS, we create a temporary buffer to
      consolidate full SG list into the buffer.
      
      We check at (TRB_CACHE_SIZE - 2) window because it is possible that there
      would be a link and/or event data TRB that take up to 2 of the cache
      entries.
      
      We discovered this issue with devices on other platforms but have not
      yet come across any device that triggers this on Linux. But it could be
      a real problem now or in the future. All it takes is N number of small
      chained TRBs. And other instances of the Synopsys IP may have smaller
      values for the TRB_CACHE_SIZE which would exacerbate the problem.
      Signed-off-by: NTejas Joglekar <joglekar@synopsys.com>
      Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
      Link: https://lore.kernel.org/r/20201208092912.1773650-3-mathias.nyman@linux.intel.comSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      2017a1e5