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  1. 17 2月, 2007 2 次提交
  3. 08 2月, 2007 2 次提交
    • S
      piix: tuneproc() fixes/cleanups · 30dfd12f
      由 Sergei Shtylyov 提交于 
      Fix/cleanup the driver's tuneproc() and ratemask() methods:

- PPE, IE, and TIME bits need to be cleared beforehand for the slave drive as
  well as master (Alan probably just forgot about it);

- this driver only supports PIO modes up to 4, so must pass the correct limit
  to ide_get_best_pio_mode();

- use min_t() macro instead of min();

- simplify slave vs master drive evaluation;

- do come coding and formatting cleanups...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      30dfd12f
    • S
      piix: fix 82371MX enablebits · d2872239
      由 Sergei Shtylyov 提交于 
      According to the datasheet, Intel 82371MX (MPIIX) actually has only a
single IDE channel mapped to the primary or secondary ports depending on
the value of the bit 14 of the IDETIM register at PCI config.  offset 0x6C
(the register at 0x6F which the driver refers to.  doesn't exist).  So,
disguise the controller as dual channel and set enablebits masks/values
such that only either primary or secondary channel is detected enabled. 
Also, preclude the IDE probing code from reading PCI BARs, this controller
just doesn't have them (it's not the separate PCI function like the other
PCI controllers), it only decodes the legacy addresses.

[ Alan sayeth " MPIIX does not work with or without the change.  It needs its
  own different driver and not to use setup-pci.  Huge job and since it works
  well with libata who cares.  Ditto the early PIIX chip." ]
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      d2872239
  5. 31 12月, 2006 2 次提交
  7. 11 12月, 2006 1 次提交
  9. 03 10月, 2006 1 次提交
    • A
      [PATCH] ide: backport piix fixes from libata into the legacy driver · 5ac24697
      由 Alan Cox 提交于 
      There are three flags being set by default by the PIIX driver for speeds >
PIO 1, and one not being cleared properly on fallback to PIO0.  The most
important one is the prefetch/post write control which only works for ATA
and can do bad things with ATAPI.

The patch does its best to set the flags correctly for drivers/ide.  Its
not 100% perfect but its closer than the original.  100% perfect requires
proper IORDY handling but this isn't critical (and its not right in libata
either ..  yet)

Sergei Shtylyov <sshtylyov@ru.mvista.com> said:

> +					{ 0, 0 },
> +					{ 0, 0 },
> +					{ 1, 0 },
> +					{ 2, 1 },
> +					{ 2, 3 }, };
>
>  	pio = ide_get_best_pio_mode(drive, pio, 5, NULL);

    BTW, there's quite obvious error here which leads to access outside of
timings[] if somebody passes PIO mode 5 (or autotuning code finds out that
drive supports PIO mode 5). Could have been fixed while at it... Those drives
should be rare, though...

> +		}
>  		master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
>  	}
>  	pci_write_config_word(dev, master_port, master_data);

    Actually, there's one more serious issue with piix_tune_drive() -- it
doesn't actually set the drive's own transfer mode.
Signed-off-by: NAlan Cox <alan@redhat.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      5ac24697
  11. 01 10月, 2006 1 次提交
  13. 01 7月, 2006 1 次提交
  15. 27 6月, 2006 1 次提交
  17. 04 2月, 2006 1 次提交
  19. 17 4月, 2005 2 次提交